Abstract: A non-volatile memory cell includes a tunneling part; a coupling device; a read transistor; a first select transistor connected to the read transistor forming a read path with the read transistor in a read mode; an erase tunneling structure forming a tunneling ejection path in an erase mode; and a program tunneling structure forming a tunneling injection path in an program mode; wherein the read path is different from the tunneling ejection path and the tunneling injection path.

Abstract: A light source system capable of dissipating heat includes a AC power supply for outputting a first power, a switch device for adjusting an output ratio of the first power according to a light setting, a light emitting device for generating a light source, and a control device for generating an active signal sequence, an heat-dissipation signal sequence and a burst signal according to lighting features of the light emitting device, and combining the active signal sequence and the heat-dissipation signal sequence, to generate a driving signal sequence, for timely outputting the driving signal sequence according to the burst signal, so as to generate the control signal.

Abstract: A method for controlling a driving circuit of a light-emitting device is disclosed. The driving circuit is utilized for transforming an input power into a driving power for the light-emitting device according to a plurality of state values. The method includes receiving the input power, outputting a first state value of the plurality of state values to the driving circuit, and outputting a second state value of the plurality of state values to the driving circuit according to variation of the input power.

Abstract: A driving device for driving a light emitting unit includes a power supply for generating power according to a control signal, an active signal generator for generating an active signal sequence according to lighting features of the light emitting unit, a heat-dissipation signal generator for generating a heat-dissipation signal sequence, a multiplexer coupled to the active signal generator and the heat-dissipation signal generator for combining the active signal sequence and the heat-dissipation signal sequence, so as to generate a driving signal sequence, a burst signal generator for generating a burst signal according to the lighting features of the light emitting unit, and a logic unit coupled to the multiplexer, the burst signal generator and the power supply for timely outputting the driving signal sequence according to the burst signal, so as to generate the control signal.

Abstract: A refresh method for a non-volatile memory for preventing disturb phenomenon includes reading data of a memory unit of the non-volatile memory at a first time point within a predefined period and storing the data in a buffer, determining whether data of the memory unit and data of the buffer are identical at a second time point within the predefined period, so as to generate a determination result, and refreshing the memory unit according to the determination result.

Abstract: A method for erasing data stored in the memory cells of the floating gate flash memory is included. The method allows a plurality of sectors to be disposed in a same P well. The method includes erasing data stored in a first set of memory cells according to a control signal, randomly reading the data stored in a second set of memory cells affected by the erasing action of the first set of memory cells, and writing data read from the second set of memory cells onto the second set of memory cells.

Abstract: When a low operation voltage device is idle and a voltage of an external power supply is larger than a predetermined voltage, a transistor with a high threshold voltage is turned on to provide electric power to the low operation voltage device. When the low operation voltage device is operating and the voltage of the external power supply is not larger than the predetermined voltage, a transistor with a low threshold voltage is turned on to provide electric power to the low operation voltage device.

Abstract: A memory structure with a repair function and a repairing method thereof are provided. The memory structure has an independent main memory unit and register file design. It also incorporates a record control unit for storing the fault information of the main memory unit. Upon receiving an access command, the memory structure determines if the main memory space pointed by the access command is faulty according to the stored fault information. When the main memory space pointed by the access command is faulty, a backup memory space is selected from the register file to replace the faulty main memory space. Therefore, the present invention can provide the convenience of a modularized design and reduce the space occupation of the register file, and also improve the access efficiency of the memory.

Abstract: A boost circuit capable of boosting a reference voltage into an output voltage. The boost circuit includes a main transistor electrically connected to the output voltage, an auxiliary transistor electrically connected to the output voltage, a pre-charge circuit electrically connected to the main transistor and the auxiliary transistor for pre-charging the main transistor and the auxiliary transistor, and a voltage detector electrically connected to the auxiliary transistor and the reference voltage for controlling the auxiliary transistor according to the reference voltage.

Abstract: A semiconductor device includes a negative voltage regulator capable of regulating a negative input voltage and outputting a negative output voltage. The negative voltage regulator has a driver for adjusting the negative output voltage, a first operational amplifier for outputting a driving voltage for controlling a current on a first transistor included in the driver according to a feedback voltage and a reference voltage, a second operational amplifier for outputting a driving voltage for controlling a current of a second transistor, a current source circuit having two triple-well NMOS transistors for providing the driver a current, and a voltage potential divider for generating the feedback voltage by dividing potentials of a voltage source and the negative output voltage and outputting the feedback voltage to the first operational amplifier and the second operational amplifier for adjusting the currents of the first and second transistors thereby regulating the negative output voltage.

Abstract: An FM demodulator has a differential output demodulator for receiving an FM signal and for outputting a positive differential signal and a negative differential signal of a demodulated signal of the FM signal, a DC offset detector electrically connected to the differential output demodulator for generating a DC offset signal according to peak signals of the positive differential signal and the negative differential signal, and a correction circuit electrically connected to the differential output demodulator and the DC offset detector to compensate for the demodulated signal according to the DC offset signal.

Abstract: A flash memory capable of utilizing one driving voltage output circuit to drive a plurality of word line drivers. The flash memory has a row driver for driving a predetermined word line to approach a predetermined voltage level. The row driver has a plurality of word line drivers, and each word line driver has a plurality of driving units and a driving voltage output circuit. The driving voltage output circuit is used for determining operating voltage levels of a plurality of driving voltages according to a plurality of second decoded signals without utilizing a plurality of first decoded signals, and for outputting a predetermined driving voltage to drive the predetermined word line to approach the predetermined voltage level when a driving unit electrically connected to the predetermined word line is turned on for connecting the predetermined word line and the driving voltage output circuit.

Abstract: A regulated charge pump has a negative charge pump for generating a first output voltage according to an oscillation signal, and a regulator. The regulator has a level shift circuit, a differential amplifier for generating a compare signal, and an oscillator for generating the oscillation signal according to the compare signal. The level shift circuit has a plurality serially connected PMOS transistors. A first PMOS transistor has a first source connected to a first reference voltage, and a gate and a drain both connected to an output end of the level shift circuit. A second PMOS has a gate and a drain both connected to an output end of the negative charge pump.

Abstract: A semiconductor device includes a negative voltage regulator capable of regulating a negative input voltage and outputting a negative output voltage at an output node. The negative voltage regulator has a driver for adjusting the negative output voltage, a first operational amplifier for outputting a driving voltage for controlling a current on a first transistor included in the driver according to a feedback voltage and a reference voltage, a second operational amplifier for outputting a driving voltage for controlling a current of a second transistor, a current source circuit having two triple-well NMOS transistors for providing the driver a current, and a voltage potential divider for generating the feedback voltage by dividing potentials of a voltage source and the negative output voltage and outputting the feedback voltage to the first operational amplifier and the second operational amplifier for adjusting the currents of the first and second transistors thereby regulating the negative output voltage.

Abstract: A negative voltage switch for use in flash memory. The switch has a control end and two voltage output ends, and includes two inverting units for transferring a positive voltage, two driving units for transferring a negative voltage, and two negative voltage pass-gate transistors for respectively transferring the negative voltage to the voltage outputs. Each inverting unit connects to a driving unit at a corresponding node, and each negative voltage pass-gate transistor connects to one of the nodes. According to a voltage at the control end, the switch turns on one inverting unit to transfer the positive voltage at the corresponding node, and the driving unit connected to the other node turns on to transfer the negative voltage to the corresponding negative voltage pass-gate transistor such that the negative voltage pass-gate transistor stops outputting the negative voltage at the other voltage output.

Abstract: A boosted clock generator has a clock generator for generating a first clock signal, a cross-coupled boost circuit electrically connected to the clock generator for boosting the first clock signal so as to generate a second clock signal, a bootstrap pass gate having an NMOSFET pass gate transistor electrically connected to the cross-coupled boost circuit for passing a higher voltage of the second clock signal, and a level shift circuit electrically connected to the bootstrap pass gate for generating a boosted clock signal according to the higher voltage of the second clock signal.

Abstract: Scribe lines for increasing a wafer utilizable area are provided. The scribe lines include at least a first scribe line arranged in a first direction in a first gap of a plurality of dies, and at least a second scribe line arranged in the first direction in a second gap of the dies. The first scribe line includes at least an alignment mark or a test key, therefore having a width greater than a width of the second scribe line that is provided for dicing a wafer into a plurality of individual dies. In addition, the scribe lines further include a plurality groups of scribe lines arranged in different directions, and each group of the scribe lines may have various scribe line widths.

Abstract: A semiconductor substrate has a V-shape structure positioned in the semiconductor substrate. A first ion implantation process is then performed to form a first doping region around the V-shape structure in the semiconductor substrate. Following this, a first dielectric layer is formed on surfaces of the semiconductor substrate and the first doping region. A floating gate is formed on the first dielectric layer over the first doping region and a second dielectric layer is formed on the floating gate, respectively. A controlling gate is then formed on the second dielectric layer. Finally, a second ion implantation process is performed utilizing the controlling gate as a mask to form a second doping region in the semiconductor substrate.