Abstract: A design method using a device with a capacitance inserted in between the output of a MOS circuit and it's corresponding load. This creates a smaller equivalence capacitance to be seen by the MOS circuit. This in turn creates faster switching times and lower power dissipation. Careful design of the circuits which have the capacitor that was added in their input stage is necessary since the high voltage level that these circuits will see is now modified due to the voltage divider created by the added capacitor and the load capacitance. With careful optimization of all parameters involved, circuits could achieve superior switching speed or superior power performance or both compared to other circuits of the same size that do not use this technique.