Abstract: A semiconductor device structure, for example a 3D structure, and a method for fabricating a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for manufacturing thereof, that comprise interposer, interlayer, and/or heat dissipater configurations that provide for low cost, increased manufacturability, and high reliability.

Abstract: A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.

Abstract: Disclosed is a semiconductor device having overlapped via apertures formed in an encapsulant to outwardly expose solder balls. When different types of semiconductor devices are electrically connected to the solder balls through the overlapped via apertures, flux or solder paste is unlikely to contact sidewall portions of the overlapped via apertures. Therefore, different types of semiconductor devices can be mounted with improved efficiency.

Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.

Abstract: Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 ?m or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof.

Abstract: A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include a semiconductor die having a first surface, a second surface opposite to the first surface, and side surfaces between the first and second surfaces; an encapsulant encapsulating the side surfaces of the semiconductor die; a contact pad on the first surface of the semiconductor die; and a redistribution layer coupled to the contact pad The redistribution layer may include a linear portion and a circular pad, and a hemispherical conductive bump on the circular pad may include a protruding part extending toward the linear portion and having a radius less than the hemispherical conductive bump. The second surface of the semiconductor die may be coplanar with a surface of the encapsulant. A dielectric layer may cover a portion of the first surface of the semiconductor die and a first surface of the encapsulant.

Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various electronic devices, and methods of making thereof, that comprise a permanently coupled carrier that enhances reliability of the electronic devices.

Abstract: A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically coupling a semiconductor die to the first redistribution layer, and forming a first encapsulant layer on the redistribution layer and around the semiconductor die. The dummy substrate may be removed thereby exposing a second surface of the first redistribution layer. A dummy film may be temporarily affixed to the exposed second surface of the redistribution layer and a second encapsulant layer may be formed on the exposed top surface of the semiconductor die, a top surface and side edges of the first encapsulant layer, and side edges of the first redistribution layer. The dummy film may be removed to again expose the second surface of the first redistribution layer, and a second redistribution layer may be formed on the first redistribution layer and on the second encapsulant layer.

Abstract: A semiconductor device with enhanced interposer quality, and method of manufacturing thereof. For example and without limitation, various aspects of the present disclosure provide an interposer die that comprises a first signal distribution structure comprising at least a first dielectric layer and a first conductive layer, wherein the signal distribution structure is protected at lateral edges by a protective layer. Also for example, various aspects of the present disclosure provide a method of manufacturing a semiconductor device comprising such an interposer die.

Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing an adhesive layer to attach an upper electronic package to a lower die and/or utilizing metal pillars for electrically connecting the upper electronic package to a lower substrate, wherein the metal pillars have a smaller height above the lower substrate than the lower die.

Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

Abstract: An encapsulated semiconductor package. As non-limiting examples, various aspects of the present disclosure provide an integrated circuit package comprising a laminate, an integrated circuit die coupled to the laminate, an encapsulant surrounding at least top and side surface of the integrated circuit die, a conductive column extending from the top side of the integrated circuit die to a top side of the encapsulant, and a signal distribution structure on a top side of the encapsulant.

Abstract: A method of forming a packaged semiconductor device includes providing a conductive frame structure. The conductive frame structure includes a first frame having leadfingers configured for directly attaching to a semiconductor device, such as an integrated power semiconductor device that includes both power devices and logic type devices. The leadfingers are further configured to provide high current capacity and a high thermal dissipation capacity for the power device portion of the semiconductor device. In one embodiment, the conductive frame structure further includes a second frame joined to the first frame. The second frame includes a plurality of leads configured to electrically connect to low power device portions of the semiconductor device. A package body is formed to encapsulate the semiconductor device and at least portions of the leadfingers and leads.

Abstract: Methods and systems for a semiconductor device with through-silicon via-less deep wells are disclosed and may include forming a mask pattern on a silicon carrier, etching wells in the silicon carrier, and forming metal contacts in the etched wells, wherein the metal contacts comprise a plurality of deposited metal layers. Redistribution layers may be formed on a subset of the contacts and a dielectric layer may be formed on the silicon carrier and formed redistribution layers. Vias may be formed through the dielectric layer to a second subset of the contacts and second redistribution layers may be formed on the dielectric layer. A semiconductor die may be electrically coupled to the second formed redistribution layers and formed vias. The semiconductor die and top surface of the dielectric layer may be encapsulated and the silicon carrier may be thinned to a thickness of the contacts or may be completely removed.

Abstract: A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise connection verification for a first one or more mounted components prior to additional assembly.

Abstract: A semiconductor package and a method of making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor packages, and methods of making thereof, that comprise a conductive layer that comprises an anchor portion extending through at least one dielectric layer.

Abstract: A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

Abstract: A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. At least one die is attached to the first surface of the substrate and positioned over the opening. A cover substrate has a plurality of metal traces. A cavity in the cover substrate forms side wall sections around the cavity. The cover substrate is attached to the base substrate so the at least one die is positioned in the interior of the cavity. Ground planes in the base substrate are coupled to ground planes in the cover substrate to form an RF shield around the at least one die.

Abstract: A semiconductor package having a second semiconductor package or module integrated therein. The semiconductor package of the present invention typically comprises active and passive devices which are each electrically connected to an underlying substrate. The substrate is configured to place such active and passive devices into electrical communication with contacts of the substrate disposed on a surface thereof opposite that to which the active and passive devices are mounted. The module of the semiconductor package resides within a complimentary opening disposed within the substrate thereof. The module and the active and passive devices of the semiconductor package are each fully or at least partially covered by a package body of the semiconductor package.

Abstract: A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.