Abstract: Method and apparatus for a display bridge with support for multiple display interfaces are disclosed. The novel display bridge comprises a predriver configured to provide data input signals. A shared output driver is configured to receive the data input signals and provide output display signals compatible for driving MIPI-DSI, EDP, or LVDS displays. A regulator and current source is coupled to the shared output driver configured to regulate the shared output driver operating voltage and provide a current source for the shared output driver. A shared termination output coupled to the shared output driver is configured to provide termination resistance for the output display signals and termination voltage for the termination resistance.

Abstract: A method to convert two-dimensional (“2D”) image content into three-dimensional (“3D”) image content for display on a display device, comprises the steps of: analyzing the 2D image content for predefined indicators and generating a depth map for each of the predefined indicators; determining a combined depth map as a function of the generated depth maps; and generating the 3D image content for display on the display device as a function of the combined depth map.

Abstract: A method for rendering video frames by a computing device having a software stack with an application layer and a kernel layer comprises various steps. First, a system reference time is initialized. A triggering of an interrupt signal in the kernel layer is waited for. Next, it is determined whether to update the system reference time as a function of a render function from the application layer. A next video frame in the kernel layer is rendered by the computing device as a function of the determined system reference time and the next video frame. The steps after the initializing step and starting at the waiting step are recursively performed.

Abstract: A method for comparing a target block to a reference window in motion estimation calculations, comprises the steps of: determining SAD calculations as a function of the target block and the reference window; reading the target block into registers; reading a segment of the reference window; updating the determined SAD calculations on the fly as a function of the read target block and the read segment of the reference window; and determining one or more sub-blocks of the reference window having minimum SAD values as a function of the updated SAD calculations; and if one or more of the minimum SAD values are not found, repeating the reading a segment step, the updating step and the determining step for a next segment of the reference window.

Abstract: A video processing system for de-interlacing a video signal comprises a motion estimation block, a refinement motion estimation block, and a de-interlacer. The motion estimation block generates integer motion vectors for the video signal. The refinement motion estimation block generates fractional motion vectors as a function of the generated integer motion vectors and select frames of the video signal. The de-interlacer generates an output as a function of the generated fractional motion vectors and the selected frames of the video signal.

Abstract: A switched capacitor digital-to-analog converter (“DAC”) for converting a digital input code to an analog signal comprises a switched capacitor array and a reset switch having a first end and a second end. The digital input code is inputted to the switched capacitor array. The switched capacitor array is connected to a summation node. The first end of the reset switch is connected to the summation node and the second end of the reset switch is connected to a common mode voltage. The reset switch is closed after a plurality of sampling cycles. The analog signal is provided based on a summation voltage at the summation node.

Abstract: A method and apparatus for a multi-core video decoder for decoding a single bitstream are disclosed. The multi-core video decoder comprises a first video decoder configured to receive the bitstream, parse header information to determine buffer management for a plurality decoding jobs based on the header information, and assign decoding jobs based upon the buffer management. A second video decoder configured to receive the bitstream and decode the bitstream based on an assigned decoding job from the first video decoder.

Abstract: A method and apparatus for processing a current macro-block of a current frame for motion compensation based on reference data from a reference frame using a sliding window cache to cache the reference data are disclosed. The method steps comprise processing a current sub-block of the current macro-block for motion compensation, determining the reference data for the current sub-block based on a reference sub-block in the reference frame, determining whether the reference data is within a sliding window, if the reference data is within the sliding window, checking for a valid tag corresponding to the reference data, responsive to the valid tag, retrieving the reference data from within the sliding window cache and processing the reference data for motion compensation.

Abstract: A method for detecting a channel bandwidth for a signal, comprises the steps of: determining a differential operator between carriers of the signal; determining a signal power for the signal; and detecting the channel bandwidth as a function of the determined differential operator and the determined signal power, wherein the signal is processed as a function of the detected channel bandwidth.