Abstract: The invention provides a method for automatically adjusting the gain of a multi-stage equalizer of a serial data receiver, the serial data receiver provides a gain circuit, the gain circuit comprises a multi-stage equalization circuit, and each stage of equalization circuit is arranged in series; the method comprises: Step S1, setting corresponding serial numbers for each stage of equalization circuit in sequence; Step S2, selecting an equalization circuit corresponding to the serial number from the gain circuit according to a preset rule; Step S3, sequentially adjusting the selected equalization circuits of each stage according to the sequence of the serial numbers to obtain corresponding standard adjustment values; and Step S4, adjusting the equalization circuit greater than or equal to the corresponding serial number according to the standard adjustment value. The method has the benefits that the optimal compensation for the signal is realized.

Abstract: The present invention discloses a method of correcting screen brightness and color temperature, it relates to the field of display technology. The present invention is used for correcting the working parameters of the every m stages of gray-level pictures to adjust display of the screen to a maximum gray level, the correction is started from a gray level next to the maximum gray level, and only for correction of the first gray level, working parameters of the previous gray level are used as the initial values of working parameters of the current gray level correction; from correction of the second gray level, a correction estimated value of working parameters of a current gray level is estimated according to the working parameters and the local linearity relation of the two corrected gray levels, and the correction estimated value is taken as the initial working parameter of the current gray level correction.

Abstract: A method for improving the security of a trusted application comprises: signing the trusted application in a hierarchical signature mode by the upper computer to generate a signature file package about the trusted application, and saving the signature file package in a main operation system; obtaining the signature file package and loading the signature file package to the second operation environment by the security execution system; parsing the signature file package by the security execution system to obtain a parsed result; and performing hierarchical verification on the parsed result by the security execution system, and if the hierarchical verification is passed, it will indicate that the trusted application is in a security state, otherwise, it is in a non-security state. The defects of lack of a security authentication mode for the trusted application and relatively low security due to mere adoption of a simple digital signature mechanism are overcome.

Abstract: The invention relates to the technical field of software systems, and more particularly, to a time division multiplexing method for decoding hardware. The method comprises: Step S1, providing a decoding hardware; Step S2, instantiating the decoding hardware into a first decoder and a second decoder; and Step S3, decoding a first data stream through the first decoder, and decoding a second data stream through the second decoder. Compared to the prior art, the present invention has the advantages that the efficiency of the decoder is improved, and the detect that the efficiency is insufficient due to the fact that the decoder runs under high-load decoding through software when the decoder is insufficient in video call application is overcome, and meanwhile, under the condition that multiple hardware decoders exist, the hardware resources are saved, and a new idea is provided for the running cost.

Abstract: The invention comprises a method for controlling a gain of a multi-stage equalizer of a serial data receiver, applied to the serial data receiver comprising the multi-stage equalizer, wherein the method comprises: Step S1, enabling the serial data receiver to receive a set of serial data; Step S2, selecting a plurality of continuous data sequences from the set of serial data according to a preset first rule; Step S3, extracting a predetermined bit from each of the plurality of continuous data sequences; Step S4, calculating an equalization gain identifier corresponding to each of the plurality of continuous data sequences according to a predetermined bit in each of the plurality of continuous data sequences; Step S5, obtaining an optimized equalization gain identifier through calculation according to each of the equalization gain identifiers; and Step S6, controlling a gain value of the multi-stage equalizer according to the optimized equalization gain identifier.

Abstract: The invention provides a method for realizing multi-channel recording based on an Android system and an audio system, wherein the audio system sequentially comprises a recording application module, an audio framework module, an audio library, a hardware abstraction module and an audio driver module in a kernel, wherein the method comprises: the hardware abstraction module calling an audio recording interface, so that the audio framework executes a multi-channel recording operation through the audio interface; the audio framework module being configured to support a multi-channel recording function; and the recording application module being configured to support transmission of multi-channel recording parameters. The requirement of a user for achieving the multi-track recording function in the Android system can be met, and the defect that in the prior art, the intelligent device, based on the Android system only supports a single-channel or double-channel recording function is overcome.

Abstract: A frequency demultiplication adjustment method of PLL comprises obtaining a plurality of corresponding frequency demultiplication frequency points according to a default frequency demultiplication value of a phase-locked loop; obtaining a load state of the processor within a predetermined sampling period, and obtaining a target frequency point of the processor by the processor frequency adjustor; determining a frequency range of a virtual frequency point to be added according to the position of the target frequency point; performing calculation within the frequency range to obtain equivalent frequencies corresponding to virtual frequency points; judging whether the frequency of the target frequency point is equal to the equivalent frequency corresponding to the virtual frequency points; if not, switching the processor frequency adjustor to the corresponding frequency demultiplication frequency point; and adjusting the frequency demultiplication value of the phase-locked loop which outputs a clock source signa

Abstract: The invention relates to the field of decoders, more specifically, to a decoding method of LDPC (Low Density Parity Check Code). The decoding method comprising: in the rwsr (Row-Wise Scanning Round) phase, the recovery circuit reads a plurality of sign bits, the absolute value of a minimum value, the absolute value of a second smallest value and the absolute value of a third smallest value which are stored previously, and they are output by a comparison and a selector, the output of the comparator and selector is shifted, and then is combined with each sign bit to obtain an update message of the previous check node, the update message is subtracted from the posterior probability by the addition circuit to obtain an input of the update unit.

Abstract: The present invention provides a method for measuring an internal Phase Locked Loop of a Central Processing Unit (CPU) by a frequency meter, wherein the method comprises following steps: the (CPU) outputting an oscillation excitation signal to a crystal circuit; the crystal signal generating a clock signal; the internal loop respectively outputting the clock signals that does not pass through and passes through the phase locked loop; adopting a frequency meter to receive the clock signals and perform a clock precision test to correspondingly obtain a first test result and a second result; comparing the first test result and the second result to obtain a result of the stability of the phase locked loop. The beneficial effects of the invention: the operation is simple and it does not need to buy an expensive oscilloscope, the accurate precision of the PLL can be measured without the influence of the crystal.

Abstract: The invention provides a phase difference generator error compensation method of a digital frequency generator, wherein the digital frequency generator comprises a phase difference generator, the phase difference generator comprises a phase compensation module and an adjusting module, the phase compensation module provides at least two clock signals, the at least two clock signals comprise a first clock signal and a second clock signal, and a phase difference exists between the first clock signal and the second clock signal; the phase compensation module outputs a third clock signal according to the first clock signal and the second clock signal, and the third clock signal is a difference signal of the first clock signal and the second clock signal; the adjusting module compensates the error of the third clock signal according to the clock phase difference. The method has the benefits that process errors in the phase difference generator are compensated.

Abstract: A television board card, a television system and a television system configuration method are disclosed. The television board card includes a storage unit configured to store a configuration file, the configuration file comprising a country code form in which a plurality of country codes are preconfigured and system configuration information corresponding to each of the plurality of country codes. The television board card further includes a receiving unit configured to receive a configuration command, and a processing unit configured to analyze the configuration file and select the corresponding system configuration information for configuration according to the configuration command.

Abstract: A phase interpolator includes a phase adjusting circuit. The phase adjusting circuit includes a first phase adjusting module and a second phase adjusting module, the first phase adjusting module outputs a first clock signal, and the second phase adjusting module outputs a second clock signal; the first phase adjustment module and the second phase adjustment module are connected in parallel to output an interpolation signal. Through the first phase adjustment module and the second phase adjustment module the first clock signal and the second clock signal with the same frequency and different phases are mixed in proportion by adopting a voltage mode to generate an interpolation so as to achieve the purpose of phase adjustment, and meanwhile, the circuit can be carried out under lower voltage, so that the power consumption of the phase adjusting circuit is further reduced.

Abstract: The invention relates to the technical field of television, and more particularly, to a data storage framework and a television device. The television device comprises a main screen and a plurality of sub-screens. The data storage framework comprises: a processor; a basic database, and a differential database, wherein the basic database is configured to store configuration data items of the main screen; the differential database is configured to store configuration data items of the plurality of sub-screens different from those of the main screen; wherein the processor is connected to the basic database and the differential database, respectively; and during display configuration of the plurality of sub-screens, the processor combines the basic database and the differential database to form a synthetic database, and outputs the synthetic database to the plurality of sub-screens. Thus, the storage data are optimized; the storage space is saved; and lower cost is realized.

Abstract: The present invention provides a method for measuring an internal Phase Locked Loop of a Central Processing Unit (CPU) by a frequency meter, wherein the method comprises following steps: the (CPU) outputting an oscillation excitation signal to a crystal circuit; the crystal signal generating a clock signal; the internal loop respectively outputting the clock signals that does not pass through and passes through the phase locked loop; adopting a frequency meter to receive the clock signals and perform a clock precision test to correspondingly obtain a first test result and a second result; comparing the first test result and the second result to obtain a result of the stability of the phase locked loop. The beneficial effects of the invention: the operation is simple and it does not need to buy an expensive oscilloscope, the accurate precision of the PLL can be measured without the influence of the crystal.

Abstract: The invention relates to a high-speed decision device that comprises a first branch and a second branch that are connected in parallel between a power supply end and a clock signal input end; wherein the first branch is used for providing a normal-phase input end, and the second branch is used for providing an inverted-phase input end; a first adjusting point and a second adjusting point are arranged; and an adjusting branch is arranged between the first adjusting point and the second adjusting point, and the adjusting branch is used for adjusting the response speed when the clock signal changes. The benefit of the invention is that the response time of the circuit is further improved, the resolution of the high-speed decision device is improved, and the clock and data recovery performance of the high-speed decision device is further improved.

Abstract: The invention provides a method for realizing multi-channel recording based on an Android system and an audio system, wherein the audio system sequentially comprises a recording application module, an audio framework module, an audio library, a hardware abstraction module and an audio driver module in a kernel, wherein the method comprises: the hardware abstraction module calling an audio recording interface, so that the audio framework executes a multi-channel recording operation through the audio interface; the audio framework module being configured to support a multi-channel recording function; and the recording application module being configured to support transmission of multi-channel recording parameters. The requirement of a user for achieving the multi-track recording function in the Android system can be met, and the defect that in the prior art, the intelligent device, based on the Android system only supports a single-channel or double-channel recording function is overcome.

Abstract: The invention provides a network outage continued playing method of an on-demand video, and an IPTV playing device, wherein the method comprises: connecting a network to acquire a data stream of the video; playing, by a player, the data stream, and obtaining a start playing time of the video; in the case of network outage, obtaining the playing time length of playing the video; when network is connected again, obtaining a time point according to the start playing time and the playing time length; searching for, by the player, according to the time point, and starting to continue to play the video at the display time label of the key frame. The present invention has the beneficial effects of directly performing the breakpoint continued playing of the on-demand video from the network outage time point when the network is connected again.

Abstract: The separating television provided in the present invention relates to the field of television and through independently configuring the master control module and the screen terminal module in the television, the screen terminal module is mainly used to play the audio and video data and control the playing, and the master control module is mainly used to receive and process the audio and video data; the master control module and the screen terminal module are independently configured in physical structure, thus allows users to carry out the operations like repair, maintenance, upgrade and replacement on them independently; especially for the extreme unmatched upgrade speed between the screen terminal device and the master control device in the field of the television, the separating television disclosed in the present application can upgrade each separate unit according to individual requirements, thus effectively reduces the upgrading cost of televisions.

Abstract: The invention relates to an implementation method of a non-radix-2-point multi data mode FFT. The implementation method comprising: using the mixed radix algorithm and prime factor decomposition algorithm to decompose the original FFT operation as the cascaded FFT operations of the multi-level programmable WFTA operations. The first-level programmable WFTA unit implements 3 point, 3 point, 5 point, and 3 point FFT operations. The second-level programmable WFTA unit implements 4 point, 5 point, 5 point, and 5 point FFT operations. The third-level programmable WFTA unit implements 9 point, 8 point, 5 point, and 9 point FFT operations. The fourth-level programmable WFTA unit implements 5 point, 5 point, 5 point, and 5 point FFT operations. The fifth-level programmable WFTA unit implements 7 point, 7 point, 7 point, and 7 point FFT operations. Each level of the programmable WFTA units is an FFT operation stage.

Abstract: The invention relates to the field of channel coding and modulation technique, more specifically, to a single-carrier channel estimation method, comprising: equalizing a carrier of an input current-frame signal and of a channel of the current-frame signal, to obtain a sequence code of the current-frame signal, decision value of transmission sequence of the current-frame signal and estimated value of signal-to-noise ratio of the current-frame signal; calculating the current-frame signal, the sequence code and the estimated value of signal-to-noise ratio to obtain a initial channel estimation; calculating the current-frame signal, the decision value of transmission sequence and the estimated value of signal-to-noise ratio to obtain a reference channel; obtaining a filtered channel value after filtering the reference channel; and obtaining the estimated channel of the next-frame signal after implementing adaptive filtering on the estimated value of initial channel and filtered channel value, by reference to the