Abstract: A system and method are provided that enables a processor to undergo a functional test of its circuits prior to attachment to a semiconductor package and prior to use in a computing platform. The method of testing chips includes attaching a non-packaged semiconductor circuit to a test bed, loading computer instructions into a memory of the non-packaged semiconductor circuit, and operating the non-packaged semiconductor circuit in a test boot mode and executing the computer instructions in that mode. The operation logs one or more events of the execution of the instructions in the test boot mode and transmits the logs of the one or more events from the non-packaged semiconductor circuit via a joint test action group (JTAG) interface or a universal asynchronous receiver/transmitter (UART) interface.

Abstract: A system and method are described herein for estimating power usage of various components of a CPU and controlling voltage regulators based on the estimated power usage. The power estimates may be based on digital power meter readings at each component, on voltage information from a voltage regulator, and on other power information. This power information is transmitted over a mesh interconnect disposed throughout the CPU such that power estimation can be accurately calculated and used to control voltage regulators without being limited by external bus speeds. More of the power management processes and components may be disposed on the CPU and connected to the mesh interconnect. These power management processes include various calibrations, adjustments, and limits so as efficiently manage and use the more rapidly processed power estimations.

Abstract: A codeword read from memory includes data blocks including data and supplemental blocks including error correction code (ECC) symbols for detecting and correcting data errors. Metadata can be stored in the supplemental blocks to increase memory utilization but using bits of the supplemental blocks for metadata leaves too few bits remaining for the ECC symbols. To maintain error protection, the supplemental blocks include ECC symbols to protect a first data portion of the codeword and parity bits configured to protect a second data portion of the codeword. Errors in the first data portion can be located and corrected using the ECC symbols. Errors in the second data portion can be detected by the parity. For example, the first data portion is encoded based on the second data portion, so locations of parity errors correspond to locations of symbol errors, and parity errors can be corrected.

Abstract: Address range memory mirroring in a computer system, and related methods and computer-readable media. The computer system includes one or more memory mirror agents that are each configured to be programmed to mirror write data of a write request to a memory address mapped to the memory mirror agent. The memory mirror agent is configured to mirror write data to a redundant memory space in memory if the write memory address is within a programmed memory space to be mirrored by the memory mirror agent. The memory mirror agent can be programmed to perform memory mirroring based on specific address ranges to provide flexibility in controlling and changing the exact memory space of the memory system to be mirrored. If an error is detected in read data in response to a memory read request, the memory mirror agent can retrieve the stored redundant data to maintain data integrity.

Abstract: Aspects disclosed include hardware micro-fused memory (e.g., load and store) operations. In one aspect, a hardware micro-fused memory operation is a single atomic memory operation performed using a plurality of data register operands, for example a load pair or store pair operation. The load pair or store pair operation is treated as two separate operations for purposes of renaming, but is scheduled as a single micro-operation having two data register operands. The load or store pair operation is then performed atomically.

Abstract: Apparatus and methods for extending functionality of memory controllers in a processor-based device are disclosed herein. In one aspect, a processor-based device provides a memory access intercept circuit that is communicatively coupled to a memory controller and a memory device. The memory access intercept circuit is configured to receive a memory write request that is directed to and received by the memory controller, and generates a write transaction identifier (ID) for the memory write request. The memory access intercept circuit then generates proxy write data containing the write transaction ID, and sends the proxy write data to the memory controller. The memory access intercept circuit subsequently intercepts the actual write data directed to the memory controller, and stores the write data in a write data buffer in association with the write transaction ID.

Abstract: Generalized boot operations for disaggregated, multiple (multi-) semiconductor die (“die”) computing system, and related methods and computer-readable media are disclosed. In exemplary aspects, to provide for generalized boot-up firmware/software for the computing system that does not have to be reconfigured for different configurations of dies in variations of IC packages, a CPU die (or other die) designated as a primary die is configured to perform a discoverable boot process over a side-band discovery bus to discover the other dies present in an IC package of the computing system and to then control their boot-up operations. In this manner, the boot-up firmware/software executed by the primary die to boot-up the computing system can be generalized irrespective of the number of dies and their particular configuration. In this manner, a generalized boot-up firmware/software can be provided to control boot-up operations of the computing system independent of specific dies included.

Abstract: Disclosed are techniques for external quiesce of a core in a multi-core system. In some aspects, a method for external quiesce of a core in a multi-core system-on-chip (SoC), comprises, at control circuitry for the multi-core SoC, receiving an indication that a core in a multi-core SoC should be quiesced, determining that the core should be externally quiesced, and asserting an external quiesce request input into the core.

Abstract: Virtualized scan chain testing in a random access memory array, and related methods and computer-readable media are disclosed. To facilitate virtualized scan chain testing, the memory array includes an integrated test circuit that causes the memory array to behave as a serialized scan chain. The integrated test circuit forces serialized write and read access to offset entries in the memory array on each scan cycle in a scan mode based on received serialized test data. After the number of scan cycles equals the number of entries the memory array, the entries in the memory array are fully initialized with test data from the serial test data flow. In subsequent scan cycles, the integrated test circuit continues to perform serial read operations to cause stored serial test data to be serially shifted out as an output serial data flow that then be compared to the original serial test data.

Abstract: A memory with data array (e.g., L2 cache) addressable in rows and columns and techniques to access data therein are proposed. Unlike conventional data arrays, the proposed memory allows data access to be initiated based on a row (or set) address even though the column (or way) address is not yet available. When the column address is determined, it can be used to select the correct data. Since the data access is started prior to determining the column address, memory access latency is reduced.

Abstract: Multi-socket computing system employing a parallelized boot architecture with partially-concurrent processor boot-up operations. In a boot of the multi-socket computing system, a first, master CPU in a master CPU socket is configured to receive a master reset signal indicating a boot-up state. In response, the first, master CPU is configured to execute a first boot program code to perform a first CPU boot-up operation. To parallelize the boot operation of a second, slave CPU in a slave CPU socket, the execution of the first boot program code by the first, master CPU includes communicating a slave boot-up synchronization signal indicating the boot-up state to the second CPU to execute a second boot program code to perform a second CPU boot-up operation. The second CPU starts to perform its CPU boot-up operation partially concurrent with the performance of the CPU boot-up operation to reduce overall boot-up time.

Abstract: Disclosed are techniques for a processing device including a mesh network connecting at least a request node device, multiple home node devices, and multiple slave node devices. In an aspect, the request node device may select a target home node device. The home node devices may be divided into M groups of home node devices. The request may be routed from the request node device to the target home node device. The target home node device may select a target slave node device from a target group of M groups of slave node devices associated with a target group of the M groups of home node devices to which the target home node device belongs. The request may be routed from the target home node device to the target slave node device.

Abstract: Methods and systems for an advanced initialization bus (AIB) are presented. In an aspect, an AIB master sends, to an AIB slave, a serial clock over a first signal line, and performs a read operation with the AIB slave. Performing the read operation comprises sending a read command to the AIB slave via a bus comprising at least one bidirectional input/output (I/O) channel, each I/O channel having its own respective signal line, sending a read address to the AIB slave via the bus, receiving a copy of the serial clock from the AIB slave over a second signal line, and latching read data provided by the AIB slave via the bus into a read buffer using the copy of the serial clock as a data strobe. Thus, the AIB master latches the read data provided by the AIB slave using a read strobe also provided by the AIB slave.

Abstract: Apparatuses, systems, and methods for configuring combined private and shared cache levels in a processor-based system. The processor-based system includes a processor that includes a plurality of processing cores each including execution circuits which are coupled to respective cache(s) and a configurable combined private and shared cache, and which may receive instructions and data on which to perform operations from the cache(s) and the combined private and shared cache. A shared cache portion of each configurable combined private and shared cache can be treated as an independently-assignable portion of the overall shared cache, which is effectively the shared cache portions of all of the processing cores. Each independently-assignable portion of the overall shared cache can be associated with a particular client running on the processor as an example. This approach can provide greater granularity of cache partitioning of a shared cache between particular clients running on a processor.

Abstract: Disclosed are techniques for performing a low-impact firmware update to a first microcontroller. In an aspect, a security entity communicatively coupled to the first microcontroller receives an update to firmware of the first microcontroller, authenticates the update to the firmware of the first microcontroller to prevent a security-related rollback, offloads system management tasks and interrupt handling from the first microcontroller to at least a second microcontroller communicatively coupled to the first microcontroller, coordinates installation of the update to the firmware of the first microcontroller without taking processing cycles from host software, and restores, to the first microcontroller, system management states occurring after the system management tasks and interrupt handling are offloaded from the first microcontroller.

Abstract: Aspects disclosed in the detailed description include multi-level instruction scheduling in a processor. Related methods and systems are also disclosed. In one exemplary aspect, an apparatus is provided that comprises a scheduler circuit comprising a scheduling group circuit, a first selection circuit, and a second selection circuit. The scheduling group circuit comprising a plurality of groups of scheduling entries, each scheduling entry among the groups of scheduling entries each comprising an instruction portion and a ready portion, each group configured to have its scheduling entries written in-order. The scheduling group circuit is further configured to maintain group age information associated with each group of the plurality of groups. The first selection circuit is configured to select a first in-order ready entry from each group. The second selection circuit is configured to select the first in-order ready entry belonging to the oldest group based on the group age information for scheduling.

Abstract: Disclosed are techniques for management of multiple processor cores in a multi-core system-on-chip (SoC). In an implementation, the SoC may configure each processor core in a first subset of processor cores as a management controller for performing system management functions for processor cores not in the first subset, the first subset comprising at least one processor core from the plurality of processor cores. System management functions are handled by the processor cores in the first subset, while operating system functions are handled by the processor cores not in the first subset. In an implementation, the number of processor cores to be included in the first subset (which may be zero if it is desired that the SoC may operate in legacy mode), may be controlled at boot time according to a boot setting.

Abstract: Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system. The processor-based system is configured to receive a cache allocation request to allocate a line in a share cache structure, which may further include a client identification (ID). The cache allocation request and the client ID can be compared to a sub-non-uniform memory access (NUMA) (sub-NUMA) bit mask and a client allocation bit mask to generate a cache allocation vector. The sub-NUMA bit mask may have been programmed to indicate that processing cores associated with a sub-NUMA region are available, whereas processing cores associated with other sub-NUMA regions are not available, and the client allocation bit mask may have been programmed to indicate that processing cores are available.

Abstract: Instruction scheduling in a processor using operation source parent tracking. A source parent is a producer instruction whose execution generates a produced value consumed by a consumer instruction. The processor is configured to track identifying operation source parent information for instructions processed in a pipeline and providing such operation source parent information to a scheduling circuit along with the associated consumer instruction. The scheduling circuit is configured to perform instruction scheduling using operation source parent tracking on received instruction(s) to be scheduled for execution. The processor is configured to compare sources and destinations for each of the instructions to be scheduled based on the operation source parent information to determine instructions ready for scheduling for execution.

Abstract: A memory control circuit stores codewords in a memory module configured to limit errors to one wire of a memory interface. A codeword includes a first block with a first data portion and a second block with a second data portion. An error correction code symbol in the second block is used to locate and correct errors in the second block. Some bits of the first block are repurposed as metadata. The remaining bits are used as parity bits for detecting errors in the first block. The second block is merged with the first block before being stored to memory and demerged from the first block in a memory read operation. Demerging causes errors in the first block to create errors in a corresponding location in the second block. The location of errors found in the second block is used to locate and correct parity errors in the first block.