Abstract: A processor array system includes an n-bit scalar processor (2) and an m x m-bit processor array (1), m and n being integers, with m greater than n. The system also includes an array support circuit (3) which is connected between the scalar processor (2) and the processor array (1) and communicates data between them. The system may include an n-bit wide data path linking n-bit scalar processor registers in the scalar processor to the array support circuit (3) together with an m-bit wide data path linking the array support circuit (3) to the processor array (1). The array support circuit (3) includes a register interface arranged to interface the n-bit scalar processor registers to the processor array (1). The array support circuit (3) also includes an m-bit wide edge registers (ME) which is connected to the processor array (1) via the m-bit wide data path. The array may employ an SIMD architecture with each of a number of single bit processing elements having associated with it local store.