Abstract: A cognitive signal converter connectable to an analog signal source via an analog signal input port and adapted to produce a digital output signal based on an analog input signal received via the analog signal input port is disclosed. The cognitive signal converter comprises an analog-to-digital converter and a cognitive network. The analog-to-digital converter is adapted to produce a digital converted signal based on the analog input signal, a sample clock signal and a process clock signal by sampling the analog input signal in accordance with the sample clock signal and quantizing each analog input signal sample, wherein the quantizing process is operated by the process clock signal.

Abstract: A time-interleaved analog-to-digital converter for conversion of L analog input signals to L corresponding digital output signals comprises an array of N (N>L) constituent analog-to-digital converters each having an analog input and a digital output and each adapted to digitize an analog input sample, and a controller adapted to (for each of the L analog input signals indexed by i=1, 2, . . . , L) select a number Ni, of constituent analog-to-digital converters from the array of N constituent analog-to-digital converters (wherein Ni?1 and ?i=1L Ni?N), and cause each sample of the analog input signal to be digitized in a respective one of the selected Ni, constituent analog-to-digital converters. The analog-to-digital converter also comprises a multiplexer adapted to (for each of the L analog input signals) multiplex the digitized samples of each of the selected Ni constituent analog-to-digital converters to produce the digital output signal.

Abstract: A method of operating a time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises, for each of at least some activations of an array of constituent analog-to-digital converters, defining first and second sets of the constituent analog-to-digital converters, feeding the analog input of each analog-to-digital converter of the first set with a reference value for imperfection measurements and clocking each analog-to-digital converter of the first set with one of the timing signals, feeding the analog input of each of analog-to-digital converter of the second set with the analog input signal for generation of an intermediate constituent digital output signal at the digital output and clocking each analog-to-digital converter of the second set with one of the timing signals, wherein no timing signal is used to clock two or more of analog-to-digital converters of the second set.

Abstract: A time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises an array of N constituent analog-to-digital converters that operate based on an analog-to-digital converter operation clock to provide the digital output signal, N sample-and-hold units connected to the input of a respective constituent analog-to-digital converter that operate based on a respective one of M of timing signals, wherein no timing signal is used to clock two or more of the sample-and-hold units, one or more digital output processing units that provide a sample of the digital output of a constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals, and a timing circuit that generates the analog-to-digital converter operation clock signal, each timing signal having a period of M/R, wherein M is less or equal to N.

Abstract: A time-interleaved analog-to-digital converter for conversion of L analog input signals to L corresponding digital output signals comprises an array of N (N>L) constituent analog-to-digital converters each having an analog input and a digital output and each adapted to digitize an analog input sample, and a controller adapted to (for each of the L analog input signals indexed by i=1, 2, . . . , L) select a number Ni of constituent analog-to-digital converters from the array of N constituent analog-to-digital converters (wherein Ni?1 and ?i=1L Ni?N), and cause each sample of the analog input signal to be digitized in a respective one of the selected Ni constituent analog-to-digital converters. The analog-to-digital converter also comprises a multiplexer adapted to (for each of the L analog input signals) multiplex the digitized samples of each of the selected Ni constituent analog-to-digital converters to produce the digital output signal.

Abstract: A method of operating a time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises, for each of at least some activations of an array of constituent analog-to-digital converters, defining first and second sets of the constituent analog-to-digital converters, feeding the analog input of each analog-to-digital converter of the first set with a reference value for imperfection measurements and clocking each analog-to-digital converter of the first set with one of the timing signals, feeding the analog input of each of analog-to-digital converter of the second set with the analog input signal for generation of an intermediate constituent digital output signal at the digital output and clocking each analog-to-digital converter of the second set with one of the timing signals, wherein no timing signal is used to clock two or more of analog-to-digital converters of the second set.

Abstract: A time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises an array of N constituent analog-to-digital converters that operate based on an analog-to-digital converter operation clock to provide the digital output signal, N sample-and-hold units connected to the input of a respective constituent analog-to-digital converter that operate based on a respective one of M of timing signals, wherein no timing signal is used to clock two or more of the sample-and-hold units, one or more digital output processing units that provide a sample of the digital output of a constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals, and a timing circuit that generates the analog-to-digital converter operation clock signal, each timing signal having a period of M/R, wherein M is less or equal to N.

Abstract: A method of determining at least one calibration value for a redundant analog-to-digital-converter, ADC, is disclosed. For at least an i:th bit bL, the corresponding bit weight wi is less than the sum of the bit weights Wj, j=0, 1, . . . , i?1 corresponding to the bits bj, j=0, 1, . . . , i?1 with lesser significance than the bit bi. The method comprises sampling a first electrical value representative of the bit weight wi; performing a first analog-to-digital, A/D, conversion using the bits bj, j=0, 1, . . . , i?1 with lesser significance than the bit bi to obtain a first digital word of said bits bj, j=0, 1, . . . , i?1 with lesser significance than the bit bi representing said first electrical value; and estimating the value of the bit weight Wi expressed in terms of the bit weights Wj. j=0, 1, . . . , i?1 corresponding to the bits bj, j=0, 1, . . .

Abstract: A method of determining at least one calibration value for a redundant analog-to-digital-converter, ADC, is disclosed. For at least an i:th bit bL, the corresponding bit weight wi is less than the sum of the bit weights Wj, j=0, 1, . . . , i?1 corresponding to the bits bj, j=0, 1, . . . , i?1 with lesser significance than the bit bi. The method comprises sampling a first electrical value representative of the bit weight wi; performing a first analog-to-digital, A/D, conversion using the bits bj, j=0, 1, . . . , i?1 with lesser significance than the bit bi to obtain a first digital word of said bits bj, j=0, 1, . . . , i?1 with lesser significance than the bit bi representing said first electrical value; and estimating the value of the bit weight Wi expressed in terms of the bit weights Wj. j=0, 1, . . . , i?1 corresponding to the bits bj, j=0, 1, . . .