Patents Assigned to Anaflash Inc.
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Patent number: 12205014Abstract: A neural network unit is disclosed.Type: GrantFiled: January 31, 2021Date of Patent: January 21, 2025Assignee: Anaflash Inc.Inventor: Seung-Hwan Song
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Patent number: 12124942Abstract: A serialized neural network computing unit is disclosed. This computing unit comprises: a bit line; a memory array having a plurality of memory blocks, each memory block have one or more than one memory cells, each cell connected to the bit line; a control circuit configured to: apply a serialized input to the memory cells in a sequence such that outputs of the memory cells are produced in a sequence in response to the serialized input, wherein each of the outputs corresponds to a multiplication of the input and a weight value stored in the memory cell; and set a group of reference current levels, each having a specific current amount, for the control circuit to control the memory cells in generating respective output currents corresponding to the set of reference current levels.Type: GrantFiled: December 1, 2020Date of Patent: October 22, 2024Assignee: Anaflash Inc.Inventor: Seung-Hwan Song
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Patent number: 11663457Abstract: A non-volatile synapse circuit of a non-volatile neural network. The synapse includes: a first input signal line for providing a first input signal; a reference signal line for providing a reference signal; first and second output lines for carrying first and second output signals therethrough, and first and second cells for generating the first and second output signals, respectively. Each of the first and second cells includes: a first upper select transistor having a gate that is electrically coupled to the first input signal line; and a first resistive changing element having one end connected to the first select transistor in series and another end electrically coupled to the reference signal line. The value of the first resistive changing element may be programmable to change the magnitude of an output signal.Type: GrantFiled: May 5, 2022Date of Patent: May 30, 2023Assignee: Anaflash Inc.Inventor: Seung-Hwan Song
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Patent number: 11361215Abstract: A non-volatile synapse circuit of a non-volatile neural network. The synapse includes: an input signal line; a reference signal line; first and second output lines, and first and second cells for generating the first and second output signals, respectively. Each of the first and second cells includes: an upper select transistor having a gate that is electrically coupled to the input signal line; and a resistive changing element having one end connected to the upper select transistor in series and another end electrically coupled to the reference signal line. The value of the resistive changing element is programmable to change the magnitude of an output signal. The drain of the upper select transistor of the first cell is electrically coupled to the first output line and the drain of the upper select transistor of the second cell is electrically coupled to the second output line.Type: GrantFiled: November 20, 2018Date of Patent: June 14, 2022Assignee: Anaflash Inc.Inventors: Seung-Hwan Song, Sang-Soo Lee
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Patent number: 11361216Abstract: A synapse circuit of a non-volatile neural network. The synapse includes: an input signal line; a reference signal line; an output line, and a cell for generating the output signal. The cell includes: an upper select transistor having a gate that is electrically coupled to the input signal line; and a resistive changing element having one end connected to the upper select transistor in series and another end electrically coupled to the reference signal line. The value of the resistive changing element is programmable to change the magnitude of an output signal. The drain of the upper select transistor is electrically coupled to the first output line.Type: GrantFiled: January 20, 2019Date of Patent: June 14, 2022Assignee: Anaflash Inc.Inventors: Seung-Hwan Song, Ji Hye Hur, Sang-Soo Lee
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Patent number: 11361802Abstract: A non-volatile memory combines a data cell and a reference cell. The data cell includes a coupling structure and a transistor stack. The transistor stack is electrically coupled to the coupling structure. The data cell can store data and output a data signal that corresponds to the data. The reference cell includes a transistor stack that has the same structure as that of the data cell and outputs a reference signal. A column circuit is electrically coupled to the data cell and the first reference cell and configured to process the data signal using the reference signal.Type: GrantFiled: February 11, 2021Date of Patent: June 14, 2022Assignee: Anaflash Inc.Inventor: Seung-Hwan Song
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Publication number: 20190311749Abstract: A non-volatile memory combines a data cell and a reference cell. The data cell includes a coupling structure and a transistor stack. The transistor stack is electrically coupled to the coupling structure. The data cell can store data and output a data signal that corresponds to the data. The reference cell includes a transistor stack that has the same structure as that of the data cell and outputs a reference signal. A column circuit is electrically coupled to the data cell and the first reference cell and configured to process the data signal using the reference signal.Type: ApplicationFiled: April 7, 2019Publication date: October 10, 2019Applicant: Anaflash Inc.Inventors: Seung-Hwan Song, Sang-Soo Lee
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Publication number: 20190164044Abstract: A non-volatile synapse circuit of a non-volatile neural network. The synapse includes: an input signal line; a reference signal line; first and second output lines, and first and second cells for generating the first and second output signals, respectively. Each of the first and second cells includes: an upper select transistor having a gate that is electrically coupled to the input signal line; and a resistive changing element having one end connected to the upper select transistor in series and another end electrically coupled to the reference signal line. The value of the resistive changing element is programmable to change the magnitude of an output signal. The drain of the upper select transistor of the first cell is electrically coupled to the first output line and the drain of the upper select transistor of the second cell is electrically coupled to the second output line.Type: ApplicationFiled: November 20, 2018Publication date: May 30, 2019Applicant: Anaflash Inc.Inventors: Seung-Hwan Song, Sang-Soo Lee
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Publication number: 20190164046Abstract: A synapse circuit of a non-volatile neural network. The synapse includes: an input signal line; a reference signal line; an output line, and a cell for generating the output signal. The cell includes: an upper select transistor having a gate that is electrically coupled to the input signal line; and a resistive changing element having one end connected to the upper select transistor in series and another end electrically coupled to the reference signal line. The value of the resistive changing element is programmable to change the magnitude of an output signal. The drain of the upper select transistor is electrically coupled to the first output line.Type: ApplicationFiled: January 20, 2019Publication date: May 30, 2019Applicant: Anaflash Inc.Inventors: Seung-Hwan Song, Ji Hye Hur, Sang-Soo Lee