Abstract: A method of WDM-aware optical routing for on-chip devices is proposed, which is executed by a computer, the method comprising using the computer to perform the following steps of: performing a path separation to identify signal net candidates; performing a path clustering to find path clusters of the signal net candidates; performing an endpoint placement to find legal locations for WDM endpoints; and performing a pin-to-waveguide routing all nets to corresponding WDM waveguides.

Abstract: A method for parasitic-aware capacitor sizing and layout generation is proposed, which is executed by a computer, the method comprising using the computer to perform the following: creating a capacitor sizing and parasitic matching sequence to represent a unit capacitor size, routing topology and routing patterns of a plural of nets in a capacitor network. Next, a shielding assignment is performed to create a number of shielding portions of each net in the plural of nets. Then, a fitness evaluation of configurations of the capacitor sizing and parasitic matching sequence is performed. A shielding net routing is performed to compensate unmatched parasitic capacitance of the configurations of the capacitor sizing and parasitic matching sequence.

Abstract: A method of redistribution layer routing for 2.5D integrated circuit packages is proposed, which is executed by a computer, the method comprising using the computer to perform the following: performing a MMSIM (modulus-based matrix splitting iteration method) based routing to assign pre-assignment nets to tracks such that total vertical distance from each bump pair to the assigned track is minimized; and performing a MWMCBM (minimum weighted maximum cardinality bipartite matching) based routing for bumps connected to the assigned tracks according to matching result to complete redistribution layer routing for integrated circuit packages.

Abstract: The method, executed by at least one processor of a computer, of an encrypting or a decrypting method for an IC layout is proposed. The encrypting method comprises getting a record of an IC layout object from a database. Data of the IC layout object is appended into a byte array. The byte array is encrypted into a second byte array. Each byte of the second byte array is defined as an encryption value to create multiple encryption values. Finally, an encryption object with multiple encryption values is created on a specified layer.

Abstract: The method, executed by at least one processor of a computer, of an encrypting or a decrypting method for an IC layout is proposed. The encrypting method comprises getting a record of an IC layout object from a database. Data of the IC layout object is appended into a byte array. The byte array is encrypted into a second byte array. Each byte of the second byte array is defined as an encryption value to create multiple encryption values. Finally, an encryption object with multiple encryption values is created on a specified layer.

Abstract: A method for redistribution layer routing is proposed. The method at least comprises inputting information regarding a redistribution layer layout, at least one netlist, and a constraint file. Next, it is creating a concentric-circle model based on the information, the netlist and the constraint file. Subsequently, it is assigning at least one pre-assignment net to at least one redistribution layer according to the concentric-circle model. Finally, the redistribution layer routing is performed.

Abstract: A method for analog circuit placement is proposed. The method comprises inputting a plurality of modules, a netlist and a constraint file. Next, it is performing a step of establishing a QB-tree construction. Then, a node perturbation of QB-tree is performed after establishing the QB-tree construction. Subsequently, it is performing a step of a look-ahead constraint checking to check whether meet constraints of the constraint file or not, followed by performing a QB-tree packing when meet constraints of the constraint file. Next, it is performing a process of performing a cost evaluation.

Abstract: A method for manipulating security of an integrated circuit layout, comprising: rendering a PCell that is created by an original user for a successive user; providing an open access to the PCell; providing a PCell evaluator to execute evaluating steps of: getting license information from the PCell, and checking the PCell license information; and generating a layout of a sub-master by instantiating a super-master of the PCell if the PCell license information is valid, or leave the sub-master empty in a PCell view if the PCell license information is invalid.

Abstract: A method and a system for constructing a customized layout figure group are disclosed. The method provides improved options for users to flexibly create a customized figure group design. During the layout process, the layout shape, the leaf device and the nest device with design parameters can be created with built-in figure groups, user's scripts and/or by capturing the user's existing layout.

Abstract: A system and method for manipulating an integrated circuit layout allowing for reuse and migration. The method comprises steps of identifying objects in a geometric layout to generate a first symbolic layout, nesting a plurality of objects in the first symbolic layout to generate a first virtual device, and associating the first virtual device to generate a second symbolic layout. The method further comprises a step of modifying parameters and constraints of the first virtual device to generate a third virtual device, and a step of optimizing a second symbolic layout including the first virtual devices to generate a third symbolic layout based on the third virtual device. Consequently, the second symbolic layout can be reused. Further, the method comprises a step of updating parameters and constraints of the first virtual device based on new process rules to generate a fourth virtual device so that the second symbolic layout can be used to generate a third symbolic layout for migration.

Abstract: A method for subdividing data of a layout, which firstly divides the layout into a plurality of to-be-processed regions so that the number of entities of each to-be-processed region is smaller then a predetermined number, and calculating an image data amount and an geometric data amount of each to-be-processed region. Then the method selects a to-be-processed region from the plurality of to-be-processed regions as a selected region, and compares the image data amount of the selected region with the geometry data amount of the selected region. When the image data amount of the selected region is larger than the geometry data amount of the selected region, the method merges the selected region with its neighboring to-be-processed region to obtain a merged region and set the merged result as a selected region. When the image data amount of the selected region is smaller than the geometry data amount of the selected region, the method sets the selected region as a subdivision of the layout.