Abstract: A high speed but power-efficient electronic communications protocol may comprise dual simplex links, each operating in a differential high-speed mode and each capable of a low-speed signaling mode. When both links operate in high speed mode, signaling is performed in-band, with signals embedded as metadata attached to transmitted packets. When one of the links is put into a low-power mode, the return-path signaling may be performed on the two wires previously used for high-speed transmissions. One wire may be used for flow control or other signaling, while the other wire may be used for a wake command, which may initiate the low-power mode to be elevated to a high-speed mode. Multiple lanes may be organized to operate in parallel for each link, allowing for a very high speed communications protocol that may be easily switched into and out of a low-power state without additional sideband wiring.

Abstract: A temperature measuring circuit uses a diode to drain a switched capacitor at two different lengths of time. The capacitor's voltage is amplified, measured, and compared for each length of time to calculate a temperature. The circuitry may cancel out errors due to manufacturing tolerances and variations, as well as offset voltages, supply noise, substrate noise, and other issues. The process may charge a capacitor, then drain the capacitor with a diode for a first period of time, at which point, the diode is switched out of the circuit. The remaining charge in the diode may be amplified, then analyzed using an analog to digital converter. A second measurement may be taken with a different period of time, and the two measurements may be subtracted to yield an absolute temperature.

Abstract: A high speed but power-efficient electronic communications protocol may comprise dual simplex links, each operating in a differential high-speed mode and each capable of a low-speed signaling mode. When both links operate in high speed mode, signaling is performed in-band, with signals embedded as metadata attached to transmitted packets. When one of the links is put into a low-power mode, the return-path signaling may be performed on the two wires previously used for high-speed transmissions. One wire may be used for flow control or other signaling, while the other wire may be used for a wake command, which may initiate the low-power mode to be elevated to a high-speed mode. Multiple lanes may be organized to operate in parallel for each link, allowing for a very high speed communications protocol that may be easily switched into and out of a low-power state without additional sideband wiring.

Abstract: A variable capacitance circuit may operate a Metal Oxide Semiconductor (MOS) transistor or other semiconductor device to switch a capacitor in and out. Several circuits may be combined in a parallel network having offset bias voltages, such that the combined network may produce a variable capacitance over a large voltage range. The variable capacitance circuit may be incorporated into a phase locked loop (PLL) circuit where similar devices may be configured to produce a voltage reference as part of the PLL circuitry. Such a circuit may be immune to temperature, process, or voltage variances, since the current pulse magnitude times the low pass filter resistance times the sensitivity of a controlled voltage oscillator can be held constant.

Abstract: A variable capacitance circuit may operate a Metal Oxide Semiconductor (MOS) transistor or other semiconductor device to switch a capacitor in and out. Several circuits may be combined in a parallel network having offset bias voltages, such that the combined network may produce a variable capacitance over a large voltage range. The variable capacitance circuit may be incorporated into a phase locked loop (PLL) circuit where similar devices may be configured to produce a voltage reference as part of the PLL circuitry. Such a circuit may be immune to temperature, process, or voltage variances, since the current pulse magnitude times the low pass filter resistance times the sensitivity of a controlled voltage oscillator can be held constant.

Abstract: A phase shift phase locked loop (PSPLL) are described. The phase shift PLL includes a PLL and a phase adjusting circuit coupled to the inputs of the PLL. The phase adjusting circuit has a first input, a first output, a second input, a third input, and a second output. The first output and the second output are coupled to a first input and a second input of the PLL, respectively. The second input of the phase adjusting circuit receives a feedback signal and the third input of the phase adjusting circuit receives a control signal. The phase adjusting circuit receives a reference signal and sends a first output signal and a second output signal based on the reference signal to the PLL to adjust a phase of an output signal of the PLL in an increment less than a time period of the output signal of the PLL.

Abstract: A method is described for encoding N variables onto less than 2N channels by forming a respective signal for each of the channels by combining inverted and/or non inverted forms of the variables, such that, each of the N variables is balanced across the channels, and, combination on any particular channel is not the polar opposite of a combination on any other channel.

Abstract: A method is described for encoding N variables onto less than 2N channels by forming a respective signal for each of the channels by combining inverted and/or non inverted forms of the variables, such that, each of the N variables is balanced across the channels, and, combination on any particular channel is not the polar opposite of a combination on any other channel.

Abstract: A phase shift phase locked loop (PSPLL) are described. The phase shift PLL includes a PLL and a phase adjusting circuit coupled to the inputs of the PLL. The phase adjusting circuit has a first input, a first output, a second input, a third input, and a second output. The first output and the second output are coupled to a first input and a second input of the PLL, respectively. The second input of the phase adjusting circuit receives a feedback signal and the third input of the phase adjusting circuit receives a control signal. The phase adjusting circuit receives a reference signal and sends a first output signal and a second output signal based on the reference signal to the PLL to adjust a phase of an output signal of the PLL in an increment less than a time period of the output signal of the PLL.