Abstract: Data isolators for providing isolation between two ports that enable dynamic communication are described. The dynamic communication may be achieved by varying a ratio of the data rate relative to a clock frequency of a clock signal. The data isolator may include a first circuit that transmits data across an isolation barrier when the clock signal is in a first state and a second circuit that transmits data across the isolation barrier when the clock signal is in a second state. The clock frequency may be variable and, as a result, change the duration of data transmissions in a given clock cycle. For example, the clock frequency may be reduced to increase the number of bits transmitted per clock cycle and, conversely, increased to reduce the number of bits transmitted per clock cycle. Thus, the number of bits transmitted per clock cycle may be adjusted to suit the situation.

Abstract: Analog circuits are often non-linear, and the non-linearities can hurt performance. Designers would trade off power consumption to achieve better linearity. An efficient and effective calibration technique can address the non-linearities and reduce the overall power consumption. A dither signal injected to the analog circuit can be used to expose the non-linear behavior in the digital domain. To detect the non-linearities, a counting approach is applied to isolate non-linearities independent of the input distribution. The approach is superior to and different from other approaches in many ways.

Abstract: A sampled analog beamformer for ultrasound beamforming includes an array of transducers for transmitting analog signals and receiving reflected analog signals, and a sampled analog filter for filtering the received reflected analog. The sampled analog filter includes a delay line for adding a delay to each of the received reflected analog signals. Using a sampled analog filter in an ultrasound beamforming system reduces the power usage of the system and decreases the number of components in the system.

Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.

Abstract: The disclosed technology generally relates to integrated circuit (IC) packages, and more particularly to integrated circuit packages comprising perforated diamond-based heat spreading substrates. In one aspect, a heat spreading substrate for an IC die is configured to be attached to an IC die and to spread heat away therefrom. The diamond-based heat spreading substrate can have an electrically conductive surface and an array of vias formed therethrough. At least one of the vias is configured to overlap an edge of the IC die when attached to the diamond-based heat spreading substrate.

Abstract: Multiplying digital-to-analog converter (MDACs) are implemented in pipelined ADCs to generate an analog output being fed to a subsequent stage. A switched capacitor MDAC can be implemented by integrating a capacitor digital-to-analog converter (DAC) with charge pump gain circuitry. The capacitor DAC can implement the DAC functionality while the charge pump gain circuitry can implement subtraction and amplification. The resulting switched capacitor MDAC can leverage strengths of nanometer process technologies, i.e., very good switches and highly linear capacitors, to achieve practical pipelined ADCs. Moreover, the switched capacitor MDAC has many benefits over other approaches for implementing the MDAC.

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

Abstract: There is disclosed in one example a digital phase-locked loop (DPLL) circuit adapted to avoid loop-bandwidth tradeoff, the circuit including: a frequency dimension frequency detector having an external frequency input and a feedback frequency input, the frequency dimension frequency detector including circuitry to measure a frequency difference between the external frequency input and the feedback frequency input and to drive an impulse signal, wherein the impulse signal is of a first species if the difference is positive and of a second species if the difference is negative; and a number-controlled oscillator (NCO) including circuitry to drive an output clock and to adjust the frequency of the output clock responsive to the impulse signal, wherein an output of the NCO provides the feedback frequency input of the frequency dimension frequency detector.

Abstract: Data isolators for providing isolation between two ports that enable dynamic communication are described. The dynamic communication may be achieved by varying a ratio of the data rate relative to a clock frequency of a clock signal. The data isolator may include a first circuit that transmits data across an isolation barrier when the clock signal is in a first state and a second circuit that transmits data across the isolation barrier when the clock signal is in a second state. The clock frequency may be variable and, as a result, change the duration of data transmissions in a given clock cycle. For example, the clock frequency may be reduced to increase the number of bits transmitted per clock cycle and, conversely, increased to reduce the number of bits transmitted per clock cycle. Thus, the number of bits transmitted per clock cycle may be adjusted to suit the situation.

Abstract: Various examples are directed to systems and methods for providing correction to cascaded signal components. A correction signal may be applied to multiple signal components in a set of cascaded signal components.

Abstract: Microelectromechanical system (MEMS) accelerometers are described. The MEMS accelerometers may include multiple proof mass portions collectively forming one proof mass. The entirety of the proof mass may contribute to detection of in-plane acceleration and out-of-plane acceleration. The MEMS accelerometers may detect in-plane and out-of-plane acceleration in a differential fashion. In response to out-of-plane accelerations, some MEMS accelerometers may experience butterfly modes, where one proof mass portion rotates counterclockwise relative to an axis while at the same time another proof mass portion rotates clockwise relative to the same axis. In response to in-plane acceleration, the proof mass portions may experience common translational modes, where the proof mass portions move in the plane along the same direction.

Abstract: A successive-approximation-register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal-independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal-independent (can be easily measured and corrected/calibrated).

Abstract: Aspects of the embodiments are directed to methods and imaging systems. The imaging systems can be configured to sense, by an light sensor of the imaging system, light received during a time period, process the light received by the light sensor, identify an available measurement period for the imaging system within the time period based on the processed light, and transmit and receive light during a corresponding measurement period in one or more subsequent time periods.

Abstract: Micromachined inertial devices are presented having multiple linearly-moving masses coupled together by couplers that move in a linear fashion when the coupled masses exhibit linear anti-phase motion. Some of the described couplers are flexural and provide two degrees of freedom of motion of the coupled masses. Some such couplers are positioned between the coupled masses. Using multiple couplers which are arranged to move in linearly opposite directions during linear anti-phase motion of the coupled masses provides momentum-balanced operation.

Abstract: Compact integrated device packages are disclosed. The package comprises a package substrate, a first integrated device die, and a second integrated device die. The first die and the second die are mounted and electrically connected to a first segment and a second segment of the package substrate respectively. The substrate comprises a bendable segment disposed between the first and second segment and can bend so as to angle the first die relative to the second die.

Abstract: There is disclosed in one example a digital phase-locked loop (DPLL) circuit adapted to avoid loop-bandwidth tradeoff, the circuit including: a frequency dimension frequency detector having an external frequency input and a feedback frequency input, the frequency dimension frequency detector including circuitry to measure a frequency difference between the external frequency input and the feedback frequency input and to drive an impulse signal, wherein the impulse signal is of a first species if the difference is positive and of a second species if the difference is negative; and a number-controlled oscillator (NCO) including circuitry to drive an output clock and to adjust the frequency of the output clock responsive to the impulse signal, wherein an output of the NCO provides the feedback frequency input of the frequency dimension frequency detector.

Abstract: One embodiment is an apparatus including a detector circuit electrically coupled between a signal source and a second circuit, the signal source generating a first signal, the detector circuit detecting a level of the first signal and generating a first control signal when the detected level of the first signal exceeds a first threshold value, and a clamping switch electrically coupled to receive the first control signal from the detector circuit, the clamping switch including a multi-terminal active device. The first control signal controls a state of the clamping switch such that the clamping switch clamps a level of a signal applied to the second circuit when the level of the first signal exceeds the first threshold value.

Abstract: Apparatus and methods for setting and clamping a node voltage are provided herein. In certain embodiments, a node control circuit includes a setting circuit for setting a voltage of a node based on a set signal. The node control circuit further includes at least one of a p-type follower clamp for clamping the node to an upper voltage limit based on an upper clamping control signal or an n-type follower clamp for clamping the node to a lower voltage limit based on a lower clamping control signal. When including both clamps, the node operates with a voltage level set by the set signal, but saturates at the upper voltage limit established by the upper clamping control signal and at the lower voltage limit established by the lower clamping control signal.

Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

Abstract: Isolators and methods for operating the same are described for opto-isolators with improved common mode transient immunity (CMTI). In some embodiments, a pair of photodetectors are provided in the opto-isolator and configured to generate photocurrents of opposite signs or directions in response to a light signal. Photocurrents from the pair of photodetectors are combined in a differential manner to represent data transmitted in a light signal, while common mode transient noise at the two photodetectors is attenuated or eliminated.