Abstract: A 16-bit D/A converter formed on a single monolithic chip and having two cascaded stages each including a 256-R resistor string DAC. The analog output voltage of the first stage is coupled to the second stage by two buffer amplifiers each formed by a non-epitaxial process using a P-type substrate. The amplifiers include NMOS and PMOS-cascoded bipolar current sources arranged to avoid the use of metallization to provide for electrical interconnections within the source.

Abstract: A monolithic IC chip having a differential amplifier comprising a pair of JFETs with their top and back gates electrically isolated to provide a low-leakage-current input to the top gates. The amplifier includes independent bias circuitry for setting the potentials of the JFET back gates to a level close to that of the top gates. This circuitry includes resistive means coupled to the source electrodes of the input JFETs, and operable to establish a low-noise bias point for the back gates. The bias circuitry includes a reference current source comprising a pair of JFETs identical to the input JFETs and arranged to provide a gate-to-source voltage to match that of the input JFETs.

Abstract: A log-amp or log-ratio circuit for producing a temperature-independent output signal corresponding to the logarithm of the ratio of a pair of input currents. The basic logarithm function is generated by a pair of opposed P-N junctions through which the respective input currents flow. Temperature compensation is effected by a circuit including a second pair of opposed P-N junctions which receive a PTAT current split between the junctions in accordance with a modulation factor proportional to the desired logarithmic function. The temperature-induced signal variations produced by the PTAT current source are equal and opposite to the temperature-induced signal variations produced in the first pair of P-N junctions, and a temperature-independent output signal is developed in accordance with the modulation factor applied to the PTAT current through the second pair of P-N junctions.

Abstract: A new process making it possible to produce stable buried Zener diodes in large-sized wafers where slow ramping of diffusion temperatures is required to avoid crystal damage and other adverse effects. The process includes an initial deep ion implantation of p type dopant (boron). A second ion implantation of n type dopant (arsenic) is made over the p type implantation. Both implantations are driven in to the required degree. An additional p type dopant diffusion is made coincident with the base formation by ion implantation to establish connection to the original deep p-doped region, and an additional n type dopant diffusion is made coincident with the emitter formation to establish connection with the n type dopant implantation.

Abstract: An analog-to-digital converter in the form of an integrated circuit providing a plurality of parallel-connected sub-converters, each producing one bit of the output word. For any sub-converter, an elongate P-type diffusion (20) serves as the base of a multiple-emitter NPN transistor. The same diffusion (20) serves as the collector of a pair of lateral PNP transistors. The lateral transistors inject current into the central diffusion, resulting in a parabolic voltage distribution along its length. A differential analog input voltage applied to the ends of the central diffusion shifts the parabolic voltage peak longitudinally along the diffusion. The multiple emitters of the NPN transistor are connected alternately to output nodes and sense the position of the parabolic voltage peak to produce the binary output.

Abstract: A CMOS DAC with means to avoid leakage current. In one embodiment, the back gates of the CMOS switches are held at -200 mV with respect to the output lines, and the logic low level to the off switch also is set at -200 mV relative to the output lines. In another embodiment, the CMOS switches are ion-implanted. In a still further embodiment, the output lines are held at a potential 200 mV more positive than the P- well of the CMOS switches.

Abstract: A four-quadrant analog multiplier comprising a first pair of transistors to handle one multiplier input and second and third pairs of transistors interconnected with said first pair to effect multiplication. Resistors are connected to the bases of the second and third pairs of transistors, and current which is proportional-to-absolute-temperature is caused to flow through the resistors. The resistors are laser-trimmed until V.sub.BE mismatch distortion is nulled. An op amp is used to drive the bases of all three pairs of transistors. A current source is connected to the first pair of transistors, and is separately controlled so as to provide for four-quadrant division. A number of additional features are incorporated to further minimize distortion and to improve performance in other respects.

Abstract: A method is disclosed for matching the sensitivities of different-sized resistors to changes in resistance due to changes in width resulting from a systematic manufacturing error. In order to produce sets of resistors which can be deployed in predetermined ratios of resistance, the sensitivities of a matching resistor and a reference resistor are equalized by forming the matching resistor as a plurality of parallel strips as opposed to a unitary rectangular section.

Abstract: A method is disclosed for matching the sensitivities of different-sized resistors to changes in resistance due to changes in width resulting from a systematic manufacturing error. In order to produce sets of resistors which can be deployed in predetermined ratios of resistance, the sensitivities of a matching resistor and a reference resistor are equalized by forming the matching resistor as a plurality of parallel strips as opposed to a unitary rectangular section.

Abstract: A precision voltage reference comprising an IC chip having a Zener diode connected to the input of an operational amplifier. Variations in output with temperature are minimized by selectively controlling the Zener current in accordance with temperature. The current is controlled by a resistive circuit including a thermistor connected in parallel with the Zener. A method of trimming the voltage reference is provided wherein an optimum quiescent operating current is determined based on voltage and current measurements at two different temperatures.

Abstract: A CMOS D/A converter for use in a voltage-mode and having complementary-driven switch pairs for V.sub.ref and A.sub.gnd respectively. The "ON" gate voltage of the A.sub.gnd switch is adjusted in accordance with the value of V.sub.ref, to give switch V.sub.GS equality and therefore "ON" resistance matching with the V.sub.ref switch over a wide range of reference voltage. Circuits are shown for developing the A.sub.gnd gate voltage varying with V.sub.ref.

Abstract: An integrated-circuit analog-to-digital converter of the successive-approximation type formed on a single monolithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I.sup.2 L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator. The inverted mode transistors provide an internal clock and successive-approximation control circuitry for the DAC. The chip also includes a voltage reference to provide for absolute analog-to-digital conversions.

Abstract: A miniaturized thick-film isolation transformer comprising two rectangular substrates each carrying successive screen-printed thick-film layers of dielectric with spiral planar windings embedded therein. The spiral windings comprise conductors formed of fused conductive particles embedded within a layer of dielectric insulating means solidified by firing at high temperature to form a rigid structure with the windings hermetically sealed within the dielectric and conductively isolated from each other within the transformer. The substrates are formed at opposite ends thereof with closely adjacent connection pads all located at a single level to accommodate automated connection making. Connections between the pads and the windings are effected by conductors formed of fused conductive particles. The substrates and the dielectric layers are formed with a central opening in which is positioned the central leg of a three-legged solid magnetic core.

Abstract: An integrated-circuit analog-to-digital converter of the successive-approximation type formed on a single monolithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I.sup.2 L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator. The inverted mode transistors provide an internal clock and successive-approximation control circuitry for the DAC. The chip also includes a voltage reference to provide for absolute analog-to-digital conversions.

Abstract: A 16-bit D/A converter formed on a single monolithic IC chip and having two cascaded stages each including a 256-R resistor-string DAC. The first stage employs a switch selector system capable of selecting any two adjacent taps of the resistor string to produce a segment voltage to be applied across the second stage resistor string. The resistor strings are formed as elongate thin film strips configured as a single, unbent body having integral voltage tap nipples evenly-spaced along both sides of the strip. Buffer amplifiers between the cascaded stages incorporate NMOS and PMOS-cascoded bipolar current sources in a non-epitaxial structure on a P-type substrate.

Abstract: A single-chip 8-bit DAC with bipolar current sources, an output buffer amplifier for developing an output voltage, a regulated reference for producing a calibrated output, and operated by a single-voltage supply, e.g. +5 volts. The buffer amplifier includes means providing for driving the output voltage virtually to ground level when the DAC output is zero. The current sources comprise a single-transistor cell driven by an I.sup.2 L flip-flop circuit, and the reference supply is merged with the reference transistor circuit regulating the DAC current levels, both aiding in reducing required chip area. A highly efficient bias network is utilized to supply the high-level bias currents required.

Abstract: A signal-controllable attenuator comprising a 17-bit multiplying-type digital-to-analog converter having an R/2R ladder network to set the bit weights, and controlled by a 6-bit remotely-generated command signal to vary the attenuation in steps of 1.5 dB through a range of 88 dB. The 1.5 dB steps are controlled by a 4-bit code signal responsive to two bits of the command signal. The 4-bit code signal is directed to four successive bit input terminals of the converter. Which four DAC input terminals are selected is controlled by a shifting matrix which shifts the four bits along the DAC input terminals to a position determined by the other four bits of the command signal.

Abstract: The new process makes it possible to produce stable buried Zener diodes in large-sized wafers where slow ramping of diffusion temperatures is required to avoid crystal damage and other adverse effects. The process includes an initial deep diffusion of p type dopant carried out in two separate steps. In the first step, a diffusion of p dopant is made and is partially driven in. Thereafter, a second diffusion of p dopant is made over the first diffusion and both diffusions are further driven in to the required degree. The Zener diode is completed by still further diffusions including an n dopant diffusion to establish a sub-surface breakdown junction with the first two p dopant diffusions. The first two p dopant diffusions use the same mask window, and preferably are made during the isolation diffusion sequence for the wafer.

Abstract: A digital-to-analog converter capable of high resolution performance, e.g. for converting 16-bit digital signals, comprising a cascaded two-stage device wherein the first stage consists of a segment converter with a series-connected string of resistors and switches operable by a set of high-order input bits for selecting the voltage across any one of the resistors, buffer amplifiers for directing the selected voltage to the input of a second-stage converter comprising a CMOS DAC with an R/2R ladder controlled by a set of lower order bits to interpolate between the limits of the selected voltage from the first stage, and wherein the switches for the first stage function to interchange the roles of the buffer amplifiers for each step up (or down) the resistor string so as to eliminate or minimize differential non-linearity errors due to offset mismatch between the buffer amplifiers.

Abstract: A digital-to-analog converter comprising an IC switch module providing four switch transistors and associated switch-control buffering circuitry. The emitter areas of the switch transistors are binarily weighted to provide equal current densities. The IC substrate also is formed with a fifth transistor to serve as a reference transistor for adjusting the supply voltage as necessary to maintain constant current through the switch transistors. To construct a digital-to-analog converter having a high bit resolution, a number of such "quad" switch modules may be combined, for example in a printed circuit card assembly including a thin-film resistor module providing binarily-weighted resistors on a glass substrate to set the current levels through the switch transistors.