Abstract: In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.

Abstract: An image processor that calculates values that are related to distortion between two image parts. The values are detected in a previous calculation. Those values are then used in the next calculation cycle to detect an early exit. That value, called least, divided by the number of accumulators, and its negative is loaded into the accumulators. When the accumulators reach zero, an early exit is established.

Abstract: An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.