Abstract: The present disclosure relates to configuring at least one pair of devices in a physical unclonable function (PUF) apparatus and reading out at least one pair of devices for determining a persistent random PUF output. The pair of devices may be readout by measuring a physical difference between the devices/components caused by random manufacturing differences, which may then be used to determine a persistence random PUF output. Configuring the pair of devices includes measuring the random manufacturing difference and, based on that measurement, setting a readout condition for the pair of devices, which dictates aspects of the readout process that should be used for that pair of devices. Each time the pair of devices is readout in the future, it may be readout in accordance with the condition that was set at configuration.

Abstract: A data channel includes a power constrained first channel portion to receive energy from a limited power source and a non-power constrained second channel portion to receive energy from a different power source than the first channel portion. The first channel portion includes an ADC circuit to output an ADC data sample, a first transmitter circuit configured to serially transmit data that includes ON bits and OFF bits, and logic circuitry configured to derive transmit data from the ADC data sample. The transmitter circuit uses more energy transmitting the ON bits than the OFF bits, and the derived transmit data has a reduced number of the ON bits from the ADC data sample. The second channel portion includes a first receiver circuit to receive the derived transmit data from the first transmitter circuit of the first channel portion.

Abstract: Systems and methods are provided for synchronizing a lower-power idle state. The systems and methods perform operations comprising: initializing, by a master physical layer (PHY) controller, a connection over a network with a slave PHY controller; during initialization, synchronizing a low power idle (LPI) timer of the master PHY controller with a LPI timer of the slave PHY controller; establishing an offset between the LPI timer of the master PHY controller and the LPI timer of the slave PHY controller; and after synchronizing the timer of the master PHY controller with the LPI timer of the slave PHY controller, establishing a link between the master PHY controller and the slave PHY controller to enable the master PHY controller and the slave PHY controller to exchange data.

Abstract: A heart monitoring system includes at least two sensors embedded in a seat, such as a driver's seat in a vehicle. One of the sensors obtains a phonocardiogram (PCG) of the driver's heart in addition to noise. Another sensor is a reference sensor that obtains a noise signal, but does not include the PCG signal. Processing circuitry receives the heart signal with the noise and the reference noise signal, and performs adaptive filtering to remove the noise from the heart signal. Further analysis detects a heart rate or other heart measurements in the heart signal, and may output an alert if a heart condition is detected.

Abstract: A package is disclosed. The package includes a carrier that comprises a first conductive layer on a first side and a second conductive layer on a second side opposite the first side. The first conductive layer comprises wire bonding pads. The package also includes a semiconductor die that is flip chip mounted on the first side of the carrier.

Abstract: A voltage monitor circuit that signals if an input voltage is above or below an internally established reference level proportional to the bandgap voltage of silicon. The voltage monitor circuit mitigates main error sources generally associated with bandgap reference generation such that high accuracy and good performance may be achieved at low power cost. The techniques allow voltage monitors (e.g., brown-out and power on reset (POR) detectors) to be implemented with higher accuracy, lower power consumption, smaller area cost, and support to lower supply voltage than other solutions.

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

Abstract: Various examples are directed to a System on a Chip (SOC) and methods of operating the same. The SOC may access firmware code from a boot Read-Only Memory (ROM) of the SOC. The firmware code may comprise a plurality of functional blocks. The SOC may determine that firmware patching is active for the SOC and access patch data from a non-volatile memory of the SOC. The SOC may determine that a first functional block of the firmware code has been patched and access first patch code from the patch data. The first patch code may be associated with the first functional block. The SOC may execute the first patch code.

Abstract: Apparatus and methods for nanoplasma switches are disclosed. In certain embodiments, a nanoplasma switching system includes a nanoplasma radio frequency (RF) switch that receives an RF signal, and a nanoplasma DC switch that receives a DC bias voltage. The nanoplasma DC switch is positioned adjacent to but spaced apart from the nanoplasma RF switch. The nanoplasma DC switch induces a nanoplasma through the nanoplasma RF switch when the DC bias voltage is set to a first voltage level. By implementing the nanoplasma switching system in this manner, DC bias to turn on or off the nanoplasma RF switch can be realized without needing to use passive components such as DC blocking capacitors, choke inductors, or baluns for isolation.

Abstract: A system for reducing clock jitter may include first jitter reducing circuitry. The first jitter reducing circuitry may be arranged between an input clock signal node carrying an input clock signal and an output clock signal node carrying an output clock signal. The first jitter reducing circuitry may include a first intermediate input clock signal node and a first intermediate output clock signal node. The first jitter reducing circuitry may include a first clock delay circuit, which may be configured to: (1) delay a first intermediate input clock signal received on the first intermediate input clock signal node by an odd integer multiple of one half of a period, and (2) invert the first intermediate input clock signal. The first jitter reducing circuitry may also include a first connection, which may be from the first intermediate output clock signal node to the first intermediate input clock signal node.

Abstract: A device to convert a detected voltage, that is indicative of current conducted by a switching circuit, to a series of electrical pulses that is indicative of electrical power dissipated by the switching circuit responsive to the current. The device includes a transconductor circuit including a first circuit to receive a reference current and a first reference voltage, and to obtain a transconductance based on an auto-generated bias current and the reference current and the first reference voltage, where a value of the transconductance is determined by the reference current and the first reference voltage. The transconductor circuit further includes a second circuit coupled to the first circuit to receive the detected voltage, and to generate a first current based on the detected voltage and the obtained transconductance.

Abstract: Systems, devices, and methods related to electrostatic discharge (ESD) protection in radio frequency (RF) switch circuitry are provided. An electrostatic discharge (ESD)-protected radio frequency (RF) switch circuitry includes a common port; at least one terminal port; a switch circuitry coupled between the common port and the at least one terminal port, wherein the switch circuitry comprises one or more transistors connected in a stacked configuration; and a first ESD protection circuitry coupled between a gate of a first transistor of the one or more transistors and a driver circuitry for the first transistor.

Abstract: Techniques are described through which continuous gapless voltage measurements can be synchronized between devices with independent clock sources on an asynchronous bus by slightly adjusting a speed of a local clock source for a period of time. Also, a read-out technique is described through which the synchronous measurements can be read out in a coherent way. These techniques can allow a high-accuracy time-average of the battery cell voltage (or fuel cell voltage) to be reconstructed, while allowing the same results to be synchronous across an entire battery stack, for use in instantaneous voltage/current diagnostics or calculations.

Abstract: An analog-to-digital converter (ADC) system for providing a calibrated voltage measurement without an external reference voltage may include an ADC circuit, including an analog ADC input and a digital ADC output. The ADC system may also include circuitry to generate a first internal reference voltage and a second internal reference voltage. The ADC system may also include circuitry configured to provide a selected output from a number of inputs, wherein the inputs include inputs to receive (1) the first internal reference voltage, (2) the second internal reference voltage, and (3) a user-provided analog signal of interest, wherein the selected output can be connected to the analog ADC input, an external voltage measurement device, or both.

Abstract: A new method and circuit arrangement for operating an electric motor, such as a stepper motor, in a control loop for preventing motor stall, the electric motor comprising at least a first motor coil and a second motor coil, the method comprising: operating the electric motor at a velocity equal to the target velocity; receiving a load value associated with an electric motor load; and determining whether the load value is greater than a load value threshold. Based on a determination that the load value is greater than the load value threshold decreasing the velocity of the electric motor to a velocity less than the target velocity.

Abstract: Apparatus and method for establishing a stable operating point of a H-bridge with a center shunt switch. The stable operating point lets a circuit connected to the H-bridge outputs work in a more ideal condition. As such, an H-bridge with a stable operating point will yield a higher performance and/or save power. Since common mode is one of the biggest sources of electromagnetic interference, a stable operating point in an H-bridge also suppresses EMI.

Abstract: Front-end circuitry is difficult to design for high sample rate, wide bandwidth receivers with high performance requirements on noise and linearity. One exemplary front-end circuitry is integrated on-chip with the RF ADC in a receiver, and the circuitry implements ESD protection, attenuation, and gain. The circuitry includes a multi-tap filter with LC circuits, and the filter implements a highly linear filter. Advantageously, the capacitors in the LC circuits are also used for ESD protection. Additionally, tunable attenuator cells are implemented across the multi-tap filter to provide a wide range of variable attenuation. The circuitry can further include a fixed or variable gain stage at the output. The resulting circuitry offers variable gain and attenuation while meeting bandwidth, noise, and linearity requirements.

Abstract: The disclosed technology generally relates to lithographically defined conductive lines for integrated circuit devices formed by plating, and more particularly to conductive lines shaped to reduce the magnitude of electric field in the electric field distributions around conductive lines of integrated and monolithic transformers and isolators.

Abstract: A charge pump is connected between a source and a body of the switch. Such a configuration avoids a condition in which the body diode opens for negative drain-to-source voltage (Vds) across the switch. Such a configuration also avoids a condition in which the switch control circuit generates control signals referenced to a body potential rather than a source potential, thereby allowing the switch to reliably turn off even for negative Vds. An additional gain stage ensures that the switch can be properly turned on. The techniques can be used to generate switches that enable highly linear processing of bipolar differential signals even far outside of the supply range.

Abstract: A load switch system and method of manufacture can include: configuring a power switch to complete or interrupt a power circuit; coupling a low current comparator for comparing the current to a low current threshold and outputting a first current threshold signal; coupling a filter to the low current comparator, the filter outputs the first current threshold signal after a predefined length of time; coupling a high current comparator to the current sensor, the high current comparator compares the current to a high current threshold and outputs a second current threshold signal; and coupling a control logic to the low current comparator and to the high current comparator, the control logic opens the power switch and interrupts the power circuit based on the second current threshold signal being output by the high current comparator or the first current threshold signal being output by the filter.