Abstract: A system has a baseband gain stage to receive incoming in-phase and quadrature voltage signals and output in-phase and quadrature current signals, a mixer core arranged to receive the in-phase and quadrature current signals and output radio frequency signals, and a variable gain amplifier to receive the radio frequency signals and produce a broadband radio signal.

Abstract: At least one embodiment provides a method for a nanopower boost regulator to startup from an ultra-low-voltage (such as 0.3V˜0.5V) for energy harvesting applications. The method does not necessarily require a special process or any external components such as mechanical switches. The startup circuit can include an asynchronous boost circuit to charge up an output with stacked power NMOS transistors, a ring oscillator, and/or a charge pump, along with accompanying circuitry.

Abstract: Battery monitors are provided in association with battery stacks to monitor the health of individual batteries. This is important as damaged batteries present a fire risk. Usually the battery stack is assembled and connected to a multipin connector assembled and connected to a multipin connector which engages with a cooperating connector of a battery monitor. The connections have a tolerance so the connections make in a random and uncontrolled order. This disclosure provides ways of ensuring that the power supply connector connects first. This reduces voltage stress in the monitoring circuit and also allows steps to be taken to control inrush currents.

Abstract: A control circuit for use with a four terminal sensor, such as a glucose sensor. The Glucose sensor is a volume product and typically its manufacture will want to make it as inexpensively as possible. This may give rise to variable impedances surrounding the active cell of the sensor. Typically the sensor has first and second drive terminals and first and second measurement terminals, so as to help overcome the impedance problem. The control circuit is arranged to drive at least one of the first and second drive terminals with an excitation signal, and control the excitation signal such that a voltage difference between the first and second measurement terminals is within a target range of voltages. To allow the control circuit to work with a variety of measurement cell types the control circuit further comprises voltage level shifters for adjusting a voltage at one or both of the drive terminals, or for adjusting a voltage received from one or both of the measurement terminals.

Abstract: One factor in limiting the speed of conventional implementations of mixture models is that the algorithm involves many decisions where different operations are fetched and performed depending on the outcome of the decisions. These decisions cause flushing of the pipeline, and thus prevent the realization of a highly parallel pipeline in a processor. Without parallelism, the throughput of the pipeline in the processor, i.e., the ability to process many samples of the digital input at a time, is limited. To alleviate this issue, implementation of the mixture model is reformulated, among other things, by embedding decisions into the process flow as multiplicative factors. The resulting implementation alleviates the need to use if-else statements for the decisions and reduces the number of times the pipeline has to be flushed. The implementation enables a pipeline with a higher degree of parallelism and thereby increases throughput and speed of the implementation.

Abstract: In an example embodiment, an analog to digital converter (ADC) facilitating passive analog sample and hold is provided and includes a pair of binary weighted conversion capacitor arrays, a pair of sampling capacitors, and a plurality of switches that configure each conversion capacitor array and the sampling capacitors for a sampling phase, a charge transfer phase, and a bit trial phase. During the sampling phase, the sampling capacitors are decoupled from the conversion capacitors and coupled to an analog input voltage. During the charge transfer phase, the sampling capacitors are coupled to the conversion capacitors and decoupled from the analog input voltage. During the bit trial phase, the sampling capacitors are decoupled from the conversion capacitors.

Abstract: In an example embodiment, an amplifier having high gain and high slew rate is provided and includes a pair of input transistors to which input voltage is applied, a pair of diode-connected loads coupled to the input transistors, at least one pair of current sources coupled to the diode-connected loads, and a bias control configured to turn off the at least one pair of current sources to enable high slew rate for the amplifier and to turn on the at least one pair of current sources to enable high gain for the amplifier. In specific embodiments, the current sources include transistors, the bias control controls a bias voltage to the current sources, and the bias voltage is driven to the supply voltage (VDD) to turn off the current sources.

Abstract: A headset driver circuit is described which comprises a connector interface. The connector interface comprises a first terminal, a second terminal and a third terminal for establishing respective electrical connections to a first speaker, a microphone and a common ground node of a headphone, earphone or headset, respectively. A first power amplifier is coupled to the first terminal to supply a first audio output signal to the first speaker of the headset. A first switch arrangement comprises a first ground switch is configured for selectively connecting and disconnecting the second terminal and a ground node of the headset driver circuit. The headset driver circuit further comprises a second ground switch configured for selectively connecting and disconnecting the third terminal and the ground node. The headset driver circuit also comprises a differential preamplifier, e.g.

Abstract: It is known to perform sample rate conversion. A sample rate converter is arranged to receive digital data at an input sample rate Fs and to output data at an output sample rate Fo, where Fo=Fs/N, and N is decimation factor greater than 1. A problem can arise with sample rate converters when a user wishes to change the decimation rate. Generally a sample rate converter needs to discard the samples in its filter when the decimation rate is changed, and the filter output is unusable until the filter has refilled with values taken at the new decimation rate. The sample rate converter provided here does not suffer from this problem. The sample rate converter includes at least Q channels.

Abstract: An oscillator for a signal isolator system includes a capacitor and an inductor connected in parallel, two pairs of cross-coupled switches and a control switch. The capacitor, the inductor and the cross-coupled switches form an oscillator. The control switch controls operation of the oscillator between an ON state and an OFF state in response to a data signal to be communicated across an isolation barrier. The inductor may be formed from a winding of an isolation transformer, which reduces component count as compared to a system that provides a separate inductor. Other embodiments may include a current-supplying kickstart circuit and a shorting transistor that can speed transition between the ON and OFF states.

Abstract: Delta-sigma modulators do not handle overload well, and often become unstable if the input goes beyond the full-scale range of the modulator. To provide overload protection, an improved technique embeds an overload detector in the delta sigma modulator. When an overload condition is detected, coefficient(s) of the delta sigma modulator is adjusted to accommodate for the overloaded input. The improved technique advantageously allows the delta sigma modulator to handle overload gracefully without reset, and offers greater dynamic range at reduced resolution. Furthermore, the coefficient(s) of the delta sigma modulator can be adjusted in such a way to ensure the noise transfer function is not affected.

Abstract: A wireless charging network system is disclosed that includes wirelessly charged sensor nodes. The wireless network system can include a gateway node configured to aggregate data from sensor nodes within a coverage area of the gateway node. The gateway node is further configured to wirelessly transmit power to the sensor nodes using a beamformed signal, wherein the gateway node adjusts the beamformed signal to maximize wireless power transfer to sensor nodes within each sector of the coverage area. Location information can be used to adjust the beamformed signal. For example, in various embodiments, the gateway node includes a beamformer sector profile table that defines channel adaptive beam profiles for the beamformed signal for each sector of the coverage area. The gateway node can use location information to define the beam profiles.

Abstract: A wireless charging platform for a wireless sensor network is disclosed, which includes a radio frequency energy distributor and data aggregator (REDDA) system configured to aggregate data from sensor nodes and wirelessly transmit power to the sensor nodes using a beamformed RF signal. The REDDA system can set a radiation pattern for the beamformed RF signal that maximizes RF energy transfer to the sensor nodes based on an environment associated with the sensor nodes. In various embodiments, the REDDA system can include an Internet of Things (IoT) interface connected to an IoT network, and the REDDA system can use information gleaned from the IoT network to set the radiation pattern.

Abstract: Digital signal processors often operate on two operands per instruction, and it is desirable to retrieve both operands in one cycle. Some data caches connect to the processor over two busses and internally uses two or more memory banks to store cache lines. The allocation of cache lines to specific banks is based on the address that the cache line is associated. When two memory accesses map to the same memory bank, fetching the operands incurs extra latency because the accesses are serialized. An improved bank organization for providing conflict-free dual-data cache access—a bus-based data cache system having two data buses and two memory banks—is disclosed. Each memory bank works as a default memory bank for the corresponding data bus. As long as the two values of data being accessed belong to two separate data sets assigned to the two respective data buses, memory bank conflicts are avoided.

Abstract: In an example, a system and method are provided for predicting in which way a requested memory address is most likely to be held in a multi-way cache, based on the last way accessed by the specified address register if available. If not available, then the system may determine that no best prediction is available. In that case, each way is read, and the superfluous values are disregarded, or a cache fill is performed as necessary. In certain embodiments, only a portion of the least significant bits of an add operation are used for way prediction in base-plus-offset addressing modes. This enables the decision to be made before the full-width add is complete, so that the clock cycle length is not unnecessarily lengthened by the prediction operation.

Abstract: The present disclosure relates to a method and apparatus for generating a voltage reference. More particularly the present disclosure relates to a methodology and circuitry configured to provide an output signal that combines a proportional to absolute temperature component with a complimentary to absolute temperature component to generate a stable output which is not temperature dependent.

Abstract: A magnetic field energy harvesting device may include an inductor and a controller. The inductor may include two inductor windings connected to each other in series, configured in winding directions and orientations to generate two voltages relative to the middle tap of inductor and out of phase with each other. The controller may switch the two voltages and may generate an approximately constant DC output voltage by alternating switching on and off switches.

Abstract: A system has a baseband gain stage to receive incoming in-phase and quadrature voltage signals and output in-phase and quadrature current signals, a mixer core arranged to receive the in-phase and quadrature current signals and output radio frequency signals, and a variable gain amplifier to receive the radio frequency signals and produce a broadband radio signal.

Abstract: Digital-to-analog converters (DACs) are used widely in electronics. The DACs are usually not ideal and typically exhibits errors, e.g., static mismatch errors. This disclosure describes a digital calibration technique for DAC static mismatch in continuous-time delta-sigma modulators (CTDSMs). The methodology utilizes the DAC unit elements (UEs) themselves to measure each other's mismatch. There are no extra circuitries except for the logic design inside DAC drivers or comparators. The methodology is an attractive calibration technique for high performance CTDSMs, especially for high speed system in multi-gigahertz range with low over-sampling rate (OSR).

Abstract: A transducer amplification circuit may include a preamplifier circuit with a signal input receiving a transducer signal to provide an amplified transducer signal comprising audible frequency components and ultrasonic frequency components. The transducer amplification circuit may include a first sigma-delta modulator configured to sample and quantize the amplified transducer signal to generate a first digital transducer signal comprising a first quantization noise signal. The first sigma-delta modulator may include a first noise transfer function having a high pass response in at least a portion of an audible frequency range to push the quantization noise signal to ultrasonic frequencies. A second sigma-delta modulator is configured to sample and quantize the amplified transducer signal to generate a second digital transducer signal comprising a second quantization noise signal.