Abstract: A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

Abstract: A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.

Abstract: A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

Abstract: A pulse width modulation (PWM) circuit has a PWM output signal that features accurate timing even in the face of interference imposed upon the control signal representative of the desired PWM duty cycle. The PWM circuit includes or has a first or switching section and a second or analog section. The second section has an operational amplifier with a summing circuit that sums two input signals, namely a triangular wave signal and the control input signal, and then amplifies the summed signal to produce a trapezoidal waveform output delivered to the second section. The first section features a two-input comparator that produces a PWM signal output with a fast transition in response to trapezoidal output fed as an input and compared to a stable reference signal. Due to the speed of the op amp, timing errors on the PWM output signal due to interference on the control signal are minimized.

Abstract: Circuits and methods to trim analog integrated circuits, such as five-pin linear voltage regulators, after packaging are disclosed. In an exemplary embodiment, a test mode input circuit determines establishment of a test mode operation of the analog integrated circuit. A register control circuit generates a data signal and a plurality of control signals. A register circuit, including an input shift register and a plurality of storage devices, receives the data signal and the control signals, programs the storage devices as directed, and generates a plurality of trim control signals based on the states of the storage devices. A trim control circuit applies the trim control signals to modify a normal operation of the packaged analog integrated circuit. The analog integrated circuit and the circuits to trim the analog integrated circuit may be included in a same package.

Abstract: A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

Abstract: Circuits and methods to turn-on a power MOSFET switch while limiting rush current delivered to a load are disclosed. In an exemplary embodiment, a sense circuit senses when the power MOSFET is enhanced by a first level and a second level. A control circuit controls application of three drive forces to the gate of the power MOSFET in response to the sense circuit. The first drive force adjusts the voltage applied to the gate at a first rate. The second drive force adjusts the voltage applied to the gate at a second rate less than the first rate. The third drive force adjusts the voltage applied to the gate at a third rate greater than the second rate. The circuit utilizes most of the allotted turn-on time to linearly control the power MOSFET enhancement, providing optimal slew rate control and limiting the rush current delivered to the load.

Abstract: An H bridge regulating system for driving an electric load includes a linear output stage and switch mode output stage connected to opposite ends of the load. The linear output stage has a linear mode amplifier and a feedback circuit, and its amplifier generates a first output signal tied to one end of the load. This output voltage is passed through a conditioning resistor to an inverting input of the linear mode amplifier. The switch mode output stage has a switch mode amplifier and a feedback circuit, and its amplifier generates a second output signal tied to the other end of the load. Its voltage signal is passed through a second conditioning resistor to an inverting input of the switch mode amplifier. Other feedback circuit elements are also provided to create three distinct regions of operations for each of the amplifiers.

Abstract: A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

Abstract: A current-limited switch contains a pilot circuit in parallel with a power MOSFET and a reference circuit containing a series of parallel circuits, each of which contains a current mirror MOSFET in parallel with a resistor. A current mirror compensation circuit contains circuitry which shorts out the parallel circuits in sequence as the current through the power MOSFET increases, thereby limiting the size of the current through the power MOSFET. In a preferred embodiment a body control circuit is connected to the power MOSFET to ensure that the body diode in the power MOSFET does not become forward-biased and thereby permit a flow of current through the power MOSFET even when it is turned off.

Abstract: A semiconductor package contains a plurality of sheet metal leads that are attached to one or more terminals on a top side of a semiconductor die. A heat sink is attached to a terminal on a bottom side of the die. Each of the leads extends across the die and beyond opposite edges of the die and is symmetrical about an axis of the die. At the locations where the leads pass over the edges of the die notches are formed on the sides of the leads which face the die, thereby assuring that there is no contact between the leads and the peripheral portion of the top surface of the die. Particularly in power MOSFETs the peripheral portion of the top surface normally contains an equipotential ring which is directly connected to the backside (drain) of the MOSFET, and hence a short between the leads on the top of the die and the equipotential ring would destroy the device. The result is a package that is extremely rugged and that is symmetrical about the axis of the die.

Abstract: A novel super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid-process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

Abstract: A current-limited switch contains a pilot circuit in parallel with a power MOSFET and a reference circuit containing a series of parallel circuits, each of which contains a current mirror MOSFET in parallel with a resistor. A current mirror compensation circuit contains circuitry which shorts out the parallel circuits in sequence as the current through the power MOSFET increases, thereby limiting the size of the current through the power MOSFET. In a preferred embodiment a body control circuit is connected to the power MOSFET to ensure that the body diode in the power MOSFET does not become forward-biased and thereby permit a flow of current through the power MOSFET even when it is turned off.

Abstract: The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon.

Abstract: A current-limited switch contains a pilot circuit in parallel with a power MOSFET and a reference circuit containing a series of parallel circuits, each of which contains a current mirror MOSFET in parallel with a resistor. A current mirror compensation circuit contains circuitry which shorts out the parallel circuits in sequence as the current through the power MOSFET increases, thereby limiting the size of the current through the power MOSFET. In a preferred embodiment a second MOSFET is used in each parallel circuit in place of the resistor.

Abstract: A laser-based optical inspection system is provided for detecting and measuring surface imperfections and warpage conditions in an optical information storage disk either during its manufacture or afterwards. The optical inspection system includes a light source, a rotatable mirror for directing a source beam from the light source along a radial line on the surface of the disk, a convex lens positioned between the mirror and the disk for focusing the source beam at the surface of said disk, and a photodetector for registering a beam being reflected from the surface of said disk, such that the reflected beam is indicative of surface imperfections in said disk. In addition, an electronic processor and controller are connected to the photodetector for processing its registered beam signals and for determining if the disk surface imperfections exceeds specified tolerances.

Abstract: A portable closable container has individually closable cells under a main lid. The container has a base with which the main lid defines an internal space. The internal space is partially filled by a plurality of side-by-side, top-to-bottom individual cells. Each of the cells is fitted with a removable cover which is hingedly mounted to the cell. The removable cover of the cell includes a tab for manipulation by the user's finger. A space is provided for a label on the cover of the cell. The components of the container are preferably composed of a polymerized material, such as polypropylene. There are two slots on the main lid which match the two feet on the base. These slots and the feet allow one container of the same kind to be stacked on the top of another without one shifting with respect to the other away from each other.