Abstract: An apparatus is described that includes a combined drive and termination circuit programmable to interface to DDR2 and DDR3 memory modules. In an exemplary embodiment the apparatus includes a combined output/termination driver, an input driver and a calibration subsystem. The combined output/termination driver includes a number of pull-up circuits and a number of pull-down circuits. One of the pull-up circuits presents a fixed output impedance. The rest of the pull-up circuits have an impedance programmable between two desired impedance values. One of the pull-down circuits presents a fixed output impedance. The rest of the pull-down circuits have an impedance programmable between two desired impedance values. The necessary number of pull-up circuits and pull-down circuits is activated in order to provide a desired driving and termination circuit such as to interface to specific impedance values as defined by the DDR2 and DDR3 interface protocol.

Abstract: The present disclosure is directed to communication systems and more specifically to communication devices having encoder and/or decoder blocks employing Low Density Parity Check Convolutional Codes (LDPC CCs). According to exemplary embodiments, improved LDPC CC techniques are disclosed to construct the syndrome former of an LDPC-CC code in a systematic way based on desired Rate (b/c), Memory (ms) and Period (T) while achieving specific Degree Distribution (dv and dc), Girth, and ACE constraints (nACE, dACE) for a desired configuration.

Abstract: The present disclosure relates to techniques used for improved LDPC encoding and encoding and associated architectures therefor. In one exemplary embodiment, a set of parity bits (p) are generated from a set of information bits (s), by storing information related to z×z sub-matrices of a first sub-matrix and of a second sub-matrix corresponding to a first and a second portion of a parity check matrix H of an LDPC code, to allow representation of the parity check matrix in a compressed form and by generating the set of parity bits p by appropriately multiplying, shifting and accumulating subsets from the set of information bits s based on the stored information, without decompressing the parity check matrix. Further relevenat techniques are also described.

Abstract: The present disclosure is directed to a device that allows the construction of multi-rate accumulative LDPC convolutional codes (LDPC CCs) based on a mother code with an arbitrary code rate. Related methods for constructing the multi-rate ALDPC-CCs are also disclosed. In one embodiment the multi rate ALDPC-CC includes an encoder for generating a first part of a codeword according to an LDPC code having a first code rate. A plurality of programmable accumulators is coupled to the encoder. The parity bit sequence produced at the output of the programmable accumulators is combined with the first part of the codeword to generate the codeword. The codeword has a second code rate that is lower than the first rate of the LDPC code. The second code rate is defined by the number of accumulators being enabled to connect to the encoder. Puncturing and rate matching techniques can further adjust the coder rate of the second codeword to a higher rate.

Abstract: The present disclosure is directed to communication systems and more specifically to communication devices having encoder and/or decoder blocks employing Low Density Parity Check Convolutional Codes (LDPC CCs). According to exemplary embodiments, improved LDPC CC techniques are disclosed to construct the syndrome former of an LDPC-CC code in a systematic way based on desired Rate (b/c), Memory (ms) and Period (T) while achieving specific Degree Distribution (dv and dc), Girth, and ACE constraints (nACE, dACE) for a desired configuration.

Abstract: Techniques are described to store and retrieve an encoded info bit stream, and appropriate first and second sets of parity bits to perform interleaving and rate matching, prior to transmission. On the receiver side, a recovery technique is provided which operates on the same principle as that of encoding, but decoding occurs in reverse. In accordance with an exemplary embodiment, three dedicated logical memories are provided for each of the encoded info bit stream and two sets of parity bits, respectively. The proposed solution provides an alternative methodology and/or hardware implementation for performing LTE compliant rate matching and de-rate matching when required to interleave info bits and parity bits.