Abstract: An analog integrated circuit is disclosed using integrated field effect transistor technology comprising a plurality of sampling and storage cells. A two-stage sampling cell design is used. The first stage incorporates a very small capacitor coupled to the input signal through a high speed gate. This gate, which is opened only by the simultaneous occurrence of row and column cells in the circuit, causes this first capacitor to capture at very high speed a sample of the analog signal under study. When all the first capture sections of the cell have captured on their capacitors a sample of the analog signal, a transfer gate is briefly opened to transfer the captured and buffered sample values to the second or storage section of the cells. This storage section incorporates a capacitor substantially larger than the capacitor in the capture section, and capable of storing the signal for a considerably longer time.