Abstract: Non-volatile SRAMs having an improved recall characteristic are disclosed. An illustrated non-volatile SRAM includes a plurality of unit memory cells arranged in an array. Each of the plurality of unit memory cells comprises a SRAM unit and a non-volatile circuit. The non-volatile circuit includes storage transistors, SONOS transistors connected to the storage transistors, and recall transistors connected to the SONOS transistors. The thickness of the gate insulation films of the recall transistors is thinner than the thickness of the gate insulation films of the storage transistors.

Abstract: Example methods of fabricating a silicon on insulator substrate are disclosed. One example method may include forming a plurality of trenches on a substrate, forming an insulation layer on the trenches, removing a portion of the insulation layer formed on the trenches to partially expose the substrate, and forming a silicon on insulator film in the substrate via the exposed portions of the substrate.

Abstract: A method for fabricating a transistor in a semiconductor device is disclosed. An example method forms an isolation region in a semiconductor substrate and sequentially deposits a pad oxide layer, a pad nitride layer and a first oxide layer on the substrate and the isolation region. The example method also patterns the first oxide layer and pad nitride layer to form a gate electrode, deposits a doped poly silicon layer, forms a doped polysilicon sidewall on the pad nitride layer and the first oxide layer, etches the pad oxide layer, sequentially deposits and planarizing a gate isolation layer, a gate nitride layer and a metal layer on the substrate to form the gate electrode. In addition, the example method forms a source, a drain, a gate plug, a source plug and a drain plug, respectively.

Abstract: A method of manufacturing an EEPROM device is disclosed. An example method forms a screen oxide film on a semiconductor substrate, forms a first ion implantation mask defining a gate insulating film forming region on the screen oxide film, and performs a first ion implantation on the semiconductor substrate and the first ion implantation mask. The example method also performs a first annealing of the semiconductor substrate, removes the screen oxide film and the first ion implantation mask, and forms a gate oxide film on the semiconductor substrate. In addition, the example method forms a second ion implantation mask defining a gate insulating film forming region on the gate oxide film, performs a second ion implantation on the semiconductor substrate and the second ion implantation mask, performs a second annealing for the semiconductor substrate, removes the second ion implantation mask; and forms a tunnel oxide film on the gate oxide film.

Abstract: A sputter etch method in the semiconductor fabrication is disclosed. A sputter etch method for etching a layer on a semiconductor substrate in a chamber by RF plasma, includes loading a substrate for conditioning into the chamber, depositing a metal coating layer on the inside wall of the chamber by sputter etching the substrate for conditioning in the chamber, unloading the substrate for conditioning from the chamber, loading the semiconductor substrate with the layer, and etching the layer on the semiconductor substrate. Accordingly, the sputter etch method can enhance a reliability for a fabrication process of a semiconductor device under the environment of the substantial decrease in impurity falling probability. In other words, the impurity falling probability can be decreased by coating a metal layer on the wall of the sputter etch chamber employing a wafer on which a barrier metal layer is deposited right before a main lot in a sputter etch process.

Abstract: A method for manufacturing a metal-oxide-semiconductor transistor prevents the occurrence of a contact spiking phenomenon. The method includes forming a metal thin film and an isolation oxidation film on a semiconductor substrate, and selectively etching the isolation oxidation film such that the isolation oxidation film is left remaining only over a field oxidation film; heat treating the semiconductor substrate to form silicide by the metal thin film in gate, source, and drain regions; removing portions of the metal thin film that is not formed into silicide, that is, removing unreacted metal thin film; removing the isolation oxidation film left remaining on the field oxidation film; and heat treating the semiconductor substrate in an oxygen environment to form the unreacted metal thin film remaining on the field oxidation film into a metal oxidation film. The present invention is related also to a semiconductor device that employs a metal-oxide-semiconductor transistor made using the method.

Abstract: To manufacture a non-volatile memory, an oxide film is deposited on a substrate, a flash device area and a logic gate area are removed and a tunnel oxide layer is stacked on an opened surface of the substrate. A first polysilicon is stacked over the resultant structure, a polish is carried out and the oxide film is removed. An LDD is formed in an upper portion of the substrate excepting an area occupied by the tunnel oxide layer, a sidewall is deposited on a side of the first polysilicon, a drain and a source are generated beneath the LDD excepting an area contacted to the sidewall and a TEOS is stacked on the resultant structure excepting the flash device area. An ONO layer is deposited over the resultant structure, a second polysilicon is stacked over the ONO layer, a polish is carried out and the TEOS is removed.

Abstract: A method of fabricating a semiconductor device is disclosed. An example method sequentially forms a gate insulation film and a sacrificial film on a semiconductor substrate. In addition, the example method forms a bowing hollow by selectively etching the sacrificial layer, forms gate material on the gate insulation film exposed through the bowing hollow and the sacrificial film, and forms a gate by anisotropically etching the gate material such that the gate material remains on an inner side wall of the bowing hollow.

Abstract: A method for manufacturing a metal-oxide-semiconductor transistor prevents the occurrence of a contact spiking phenomenon. The method includes forming a metal thin film and an isolation oxidation film on a semiconductor substrate, and selectively etching the isolation oxidation film such that the isolation oxidation film is left remaining only over a field oxidation film; heat treating the semiconductor substrate to form silicide by the metal thin film in gate, source, and drain regions; removing portions of the metal thin film that is not formed into silicide, that is, removing unreacted metal thin film; removing the isolation oxidation film left remaining on the field oxidation film; and heat treating the semiconductor substrate in an oxygen environment to form the unreacted metal thin film remaining on the field oxidation film into a metal oxidation film. The present invention is related also to a semiconductor device that employs a metal-oxide-semiconductor transistor made using the method.

Abstract: A semiconductor device having an interlayer insulation film with a low capacitance and a method of fabricating the same are disclosed. An example semiconductor device having a multi-layered metal wire structure includes first and second interlayer insulation films provided between lower metal wire layers and upper metal wire layers. The example semiconductor device also includes air gaps formed in the first interlayer insulation film at an interlevel between the upper and lower metal wire layers and via holes connecting the upper and lower metal wire layers.

Abstract: A manufacturing method for a non-volatile memory device includes the steps of forming a well and a channel in a silicon substrate, depositing a tunnel oxide layer, a first polysilicon layer and a nitride layer sequentially, and then performing a trench etching thereof to thereby form a self-align flash memory device.

Abstract: In a method for forming a dual damascene structure in a semiconductor device, an insulating layer is formed on a semiconductor substrate and a silicon nitride etch stop layer is formed on the insulating layer. Then a photoresist layer is applied on the etch stop layer for a contact hole pattern. Thereafter, the insulating layer is etched according to the contact hole pattern and the rest etch stop layer is pull back etched to expose upper surface of the insulating layer. The insulating layer is etched again according to the modified pattern of the rest etch stop layer and the rest etch stop layer is removed so that a dual damascene structure is completed. Therefore, a dual damascene structure can be made by using a single photoresist process and a single etch stop layer so that a manufacturing process is simplified.

Abstract: A method for fabricating a flash memory includes forming a tunnel oxide layer by depositing a material with a conduction band energy level lower than that of SiO2 on a semiconductor substrate; forming a floating gate by depositing polysilicon on the tunnel oxide layer; forming an intergate dielectric layer on the floating gate; forming a control gate on the intergate dielectric layer; forming a gate electrode by patterning the tunnel oxide layer, the floating gate, the intergate dielectric layer and the control gate; and forming a source/drain region by implanting impurities into the substrate using the gate electrode as a mask.

Abstract: A semiconductor device and fabrication method thereof that uses a far ultraviolet ray photolithography, which may be used to prevent the lift phenomenon of a photoresist pattern, is disclosed. The semiconductor device may be fabricated by the process of: forming a film which is an object of forming a pattern on a structure of a semiconductor substrate; forming a anti-reflection layer on the film to form a stacking structure including the film and the anti-reflection layer; performing a plasma treatment to form grooves on a upper surface of the stacking structure; forming a photoresist pattern on the stacking structure on which the grooves are formed; and etching the stacking structure using the photoresist pattern as a mask to form a stacking structure pattern.

Abstract: A method of fabricating a metal interconnection of semiconductor device is disclosed. A metal interconnection fabricating method according to the present invention comprises the steps of depositing a metal layer on a substrate having a predetermined structure; patterning a bottom metal layer through etching the metal layer; forming a pad electrically connecting the bottom metal layer to a scribe area; forming an insulating layer on the substrate including the bottom metal layer; forming a via hole and a trench, in which an upper metal layer is formed, on the insulating layer, the via hole connecting the bottom metal layer with the upper metal layer; forming a plating layer by means of electroplating; and performing a planarization process for the plating layer. Accordingly, the present invention needs not a separate seed layer because the bottom metal layer is used as a seed layer.

Abstract: A semiconductor device and fabrication method thereof that uses a far ultraviolet ray photolithography, which may be used to prevent the lift phenomenon of a photoresist pattern, is disclosed. The semiconductor device may be fabricated by the process of: forming a film which is an object of forming a pattern on a structure of a semiconductor substrate; forming a anti-reflection layer on the film to form a stacking structure including the film and the anti-reflection layer; performing a plasma treatment to form grooves on a upper surface of the stacking structure; forming a photoresist pattern on the stacking structure on which the grooves are formed; and etching the stacking structure using the photoresist pattern as a mask to form a stacking structure pattern.

Abstract: A method for inspecting an insulator with a library of optic images is disclosed. The method for inspecting an insulating layer according to the present invention, comprises the steps of collecting standard data for thickness of the insulating layer; collecting standard data for an optic image of the insulating layer; making a library by matching standard data for the thickness and the optic image; and inspecting the insulating layer with the library. Thus, the method of inspecting an insulating layer by using the thickness and the library of optic images in the present invention can considerably improve the conventional methods that depend only on the thickness or the optic images by making the thickness and the optic image for the part or whole of the wafer into a form of data, matching them, and making a library of them.

Abstract: A cell transistor of a flash memory device includes a semiconductor substrate, a source region, a drain region, a floating gate, an inter-gate insulating layer, and a control gate, wherein the floating gate has a tip protruding into an end portion of the source region. With the application of erasing voltages to the source region and the control gate, an intense electric field is induced on the tip of the floating gate. Accordingly, an erasing efficiency of the cell transistor can be enhanced.

Abstract: A fabrication method of a semiconductor device includes forming an interlayer dielectric film over an entire surface of a semiconductor substrate that includes a lower line. A barrier layer having an etching rate that is lower than an etching rate of the interlayer dielectric film is formed on the interlayer dielectric film. The barrier layer is selectively etched to expose a predetermined region of the interlayer dielectric film. Next, a photoresist pattern is formed on the barrier layer having an opening of a predetermined area corresponding to the exposed region of the interlayer dielectric film. The opening of the photoresist pattern has an area that is greater than an area of the exposed region of the interlayer dielectric film. The line opening and the via are then simultaneously formed by etching the exposed regions of the barrier layer and the interlayer dielectric film. Finally, a metal plug is formed by filling the line opening and the via with a metal material.

Abstract: A method for forming a metal interconnect of a semiconductor device defined by a fine trench or via is disclosed. The method includes forming a first interconnect insulating layer on a substrate. A via hole is formed on a predetermined portion of the first interconnect insulating layer. A second interconnect insulating layer is formed on the first interconnect insulating layer. The second interconnect insulating layer is planarized. A hard mask layer is formed on the second interconnect insulating layer. The hard mask layer is patterned to remove selective portions. A trench is formed by etching the second interconnect insulating layer. A metal interconnect is formed in the trench.