Abstract: A wafer scale integrated circuit comprises a few hundred modules (10) which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs (XINN, XINE, XINS, XINW) from neighboring modules and outputs thereto (XOUTN, XOUTE, XOUTS, XOUTW), only one of which is enabled by one of four selection signals (SELN, SELE, SELS, SELW) acting both on transmit path logic (20) and on receive path logic (21) in a return path. Each module includes configuration logic (22) which decodes commands providing the selection signals (SELN, etc), a READ signal and a WRITE signal. The configuration logic (22) is addressed when a bit is presented thereto by the transmit path simultaneously with assertion of a signal (CMND) which is supplied globally to all modules. The address configuration logic clocks the bit along a shift register and the selected command is determined by the position of the bit at the time that the global signal (CMND) is terminated.

Abstract: The wafer scale integrated circuit comprises an array of undiced chips or modules, each of which includes a data storing or processing circuit, e.g. a dynamic RAM, and configuration logic. Channels for data and control signals exist between each module and its (N, S, E and W) neighbors and a target module in the array may be addressed by setting up a path through the array from an entry module to the target module. The addressing is effected by sending a stream of link commands, each of which tells a module to link on to its (N, S, E or W) neighbor. Each module responds to the first command of the stream and then sends on the stream stripped of this first command. In an alternative embodiment the link commands are transmitted from module to module in parallel, each module responds to the command at the least significant end and strips it off by a shift of the commands in the least significant direction before the commands pass to the next module.

Abstract: A wafer-scale integrated circuit comprises a few hundred modules which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs XINN, XINE, XINS, XINW from neighbouring modules and outputs thereto XOUTN, XOUTE, XOUTS, XOUTW, only one of which is enabled to by one of four selection signals SELN, SELE, SELS, SELW acting both on transmit path logic and on receive path logic in a return path. A RAM unit can be enabled by WRITE to write a block of data sent to RID via the transmit path and can be enabled by READ to read a block of data to ROD for return along the return path. The provision of SELN, etc. READ and WRITE is effected by configuration logic which includes a shift register and is responsive to a command mode signal CMND, on a line which runs to all modules in parallel. If, when CMND is asserted the bit currently in the transmit path is logic (, the module is not addressed.

Abstract: An electrical data storage element which provides for alteration of this stored data by way of a data line and address lines. Data is held as a charge set on a charge storage device. The state of the switch elements is sensed by way of the data line and address line.

Abstract: A digital computer can write a block of data to a RAM, or read a block therefrom, via a serial/parallel converter which is word serial, bit parallel on the computer side and bit serial on the RAM side. The RAM is addressed by a free-running address counter clocked by clock pulses WCK. A fault masking circuit enables faulty cells in the RAM to be masked out. Data specific to the RAM causes the clock pulses WCK to be selectively gated for providing bit rate clock pulses GCK to the converter. These pulses are divided down to produce pulses BCK at word rate. The invention is particularly useful in a wafer scale integrated circuit comprising a large number of RAMs served by a single fault masking circuit with tabulated data defining the memory cells to be masked out on a memory by memory basis.

Abstract: A wafer-scale integrated circuit comprises a few hundred modules which can be connected into a long chain by commands sent from a terminal XMIT to the modules along a transmit path set up by way of module inputs from neighbouring modules and outputs thereto, only one of which is enabled by one of four selection signals. The transmit path normally follows a route through a main chain of modules M0 to M15, as shown by a full line. However, commands may be sent to nodal modules M0, M6 and M10 to make a alternative direction selections thereat, so as to obtain access to modules M16 etc in spur chains. Commands are addressed to the modules in accordance with their distances F from XMIT. Spurs may themselves include nodal modules such as M17. The normal and alternative direction selections are listed in a stored table which is used by a command unit to access any desired module and then restore the main chain M0-M15.