Abstract: A data driver circuit and a delay-locked loop (DLL) are provided. The data driver circuit and DLL can operate normally in spite of errors, etc., caused when an analog data signal is applied to a display panel. The DLL, which receives a first clock signal and outputs a second clock signal, includes a phase detector for outputting a phase difference signal according to the first clock signal, the second clock signal and at least one delay signal, and a delay line for generating the second clock signal and the delay signal by delaying the first clock signal. Here, the phase difference signal has a value corresponding to a phase difference between the first clock signal and the second clock signal, according to the first clock signal or the second clock signal, and a value corresponding to a case in which there is no phase difference according to the delay signal, and a first delay that is a delay of the second clock signal with respect to the first clock signal changes according to the phase difference signal.

Abstract: Provided are a data driving circuit, a display device, and a data driving method. The data driving circuit includes a clock generator configured to generate a clock signal from clock information included in a reception signal including the clock information, mode information and a body, a sampler configured to sample the reception signal according to the clock signal to obtain the mode information and the body that includes at least one of control information and data, a signal controller configured to determine whether or not the body corresponds to the control information with reference to the mode information, and generate a control signal corresponding to the control information according to a result of the determination, and a data driver configured to generate a data signal corresponding to the data according to the control signal.

Abstract: Provided are a display device and method. The display device includes a plurality of data driving integrated circuits (ICs) configured to receive reception signals, each of which includes data and load signal information indicating an application starting time point of the data, and apply parallel data signals corresponding to the data at the application starting time points according to the load signal information included in the reception signals, and a display panel configured to display an image according to the parallel data signals, wherein at least two of the data driving ICs apply parallel data signals at different application starting time points.

Abstract: A clock recovery circuit and a method for reducing electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers said modulated clock frequency signed to generated an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.

Abstract: A clock recovery circuit and a method for reducing electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers the modulated clock frequency signed to generated an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.