Abstract: An electronic device includes a CPU, an acceleration module, and a memory. The acceleration module is communicatively connected with the CPU, and includes chips. The chip according to an embodiment includes a data bus, and a memory, a data receiver, a computing and processing unit, and a data transmitter connected to the data bus. The data receiver receives first data and header information from outside, writes the first data to a corresponding area of the memory through the data bus, and configures a corresponding computing and processing unit and/or data transmitter according to the header information. The computing and processing unit receives first task information, performs an operation processing according to the first task information and a configuration operation on the data transmitter. The data transmitter obtains second task information and second data, and outputs third data to outside based on at least part of the second data.

Abstract: The present disclosure relates to a deep learning algorithm compiling method and a device and a related product, the product comprising a controller unit, and the controller unit comprising: an instruction cache unit, an instruction processing unit, and a queue-storing unit. The instruction cache unit is configured to store computation instructions associated with artificial neural network operations. The instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions. The queue-storing unit is configured to store an instruction queue, which comprises: a plurality of operation instructions or computation instructions to be executed according to the front-to-rear sequence of the queue. By means of the described method, the present disclosure may improve the operation efficiency of the related product when carrying out neural network model operations.

Abstract: Embodiments of the present disclosure provide a neural network processing method, a neural network processing apparatus, a computer device, and a storage medium. By splitting one operator into a plurality of sub-operators with smaller scales, a calculation library under a single-core structure may be invoked directly, which may make full use of hardware resources of a multi-core processor, thereby avoiding extra workloads brought by reimplementation.

Abstract: Embodiments of the present disclosure provide a method for splitting a neural network model to be processed by a multi-core processor and related products. When a splittable operator is present in the neural network model, the operator is split, and an optimal splitting combination is selected to obtain an optimal splitting result of an entire neural network model, and then sub-operators corresponding to the optimal splitting result are executed through multiple cores in parallel. Thereby, a purpose of reducing resource consumption of a computer device is achieved.

Abstract: Embodiments of the present disclosure provide a method for neural network processing, a neural network processing apparatus, a computer device and a storage medium. By splitting an operator into a plurality of operators with smaller scales, a calculation library under a single-core structure may be directly invoked by a multi-core processor, which makes full use of hardware resources of the multi-core processor.

Abstract: Embodiments of the present application disclose a method of performing splitting in a neural network model by means of a multi-core processor, and related products. The method includes when a splittable operator is present in the neural network model, splitting the operator, and selecting an optimal splitting combination to obtain an optimal splitting result of the entire neural network model, and then executing the sub-operators corresponding to the optimal splitting result through multi-core parallel processing. The disclosed method thus achieves the purpose of reducing resource consumption of a computer device.