Abstract: An apparatus includes a test head frame and a tray slidably coupled to the frame and configured to receive a printed circuit board (PCB) to be tested. The PCB is positioned within the frame when the tray is in a retracted position and outside the frame when the tray is in an ejected position. A bed of nails (BON) opposes a lower side of the PCB and includes a plurality of pins having first portions arranged on an upper side of the BON to connect with corresponding electrical pads on the lower side of the PCB when the tray containing the PCB is in the retracted position. A plurality of interface printed circuit boards is configured for connection to second portions of the plurality of pins exposed on a lower side of the BON and for receiving test signals when the tray containing the PCB is in the retracted position.

Abstract: An apparatus includes a test head frame and a tray slidably coupled to the frame and configured to receive a printed circuit board (PCB) to be tested. The PCB is positioned within the frame when the tray is in a retracted position and outside the frame when the tray is in an ejected position. A bed of nails (BON) opposes a lower side of the PCB and includes a plurality of pins having first portions arranged on an upper side of the BON to connect with corresponding electrical pads on the lower side of the PCB when the tray containing the PCB is in the retracted position. A plurality of interface printed circuit boards is configured for connection to second portions of the plurality of pins exposed on a lower side of the BON and for receiving test signals when the tray containing the PCB is in the retracted position.

Abstract: Technologies and methods for detecting voltage spikes on a semiconductor device include detecting a voltage spike in a first analog signal from a semiconductor device based on a comparison of the first analog signal and a first voltage threshold, and converting the first analog signal to a digital signal with a first pulse representing the voltage spike, and transforming the first pulse to a stretched pulse defining a greater width than the first pulse. More specific embodiments include receiving a second analog signal from a first pin on the semiconductor device during a capture time period, receiving a reference analog signal from a reference pin on the semiconductor device during the capture time period, and prior to detecting the voltage spike, generating the first analog signal by computing a difference between the second analog signal and the reference analog signal.

Abstract: An example method for determining test conditions for at-speed transition delay fault tests on semiconductor devices is provided and includes analyzing scan patterns for testing a circuit of a device-under-test (DUT), identifying paths in the circuit activated by the scan patterns, determining behavior of the paths at different test corners, generating a histogram for each scan pattern representing a distribution of paths exhibiting worst-case behavior at corresponding test corners, generating an ordered set of scan pattern-test corner combinations based on the histogram, selecting a threshold for the ordered scan pattern-test corner combinations based on quality metrics, generating an ordered test set including the ordered scan pattern-test corner combinations with the selected threshold, and feeding the ordered test set to a test instrument, the test instrument testing the DUT according to the ordered test set, the tests being performed at the test corners listed above the selected threshold.