Patents Assigned to ANTAIOS
  • Patent number: 11514963
    Abstract: A SOT-MRAM cell, comprising at least one magnetic tunnel junction (MTJ) comprising a tunnel barrier layer between a pinned ferromagnetic layer and a free ferromagnetic layer; a SOT line, extending substantially parallel to the plane of the layers and contacting a first end of said at least one MTJ; at least a first source line connected to one end of the SOT line; at least a first bit line and a second bit line, wherein the SOT-MRAM cell comprises one MTJ, each bit line being connected to the other end of the MTJ; or wherein the SOT-MRAM cell comprises two MTJs, each MTJ being connected to one of the first bit line and second bit line.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: November 29, 2022
    Assignee: Antaios
    Inventors: Marc Drouard, Julien Louche
  • Patent number: 11380839
    Abstract: A magnetic memory (MRAM) cell, comprising: a first layer formed from a substantially electrically conductive material; and a magnetic tunnel junction (MTJ) stack formed over the first layer, wherein the MTJ stack comprises: a ferromagnetic reference layer having an in-plane reference magnetization; a tunnel barrier layer; and a ferromagnetic storage layer between the tunnel barrier layer and the first layer, the storage layer having an in-plane storage magnetization; wherein the MTJ stack comprises an arrangement for providing an in-plane uniaxial anisotropy in the storage layer; wherein said in-plane uniaxial anisotropy makes an angle with the direction of the write current that is between 5° and 90°, and wherein said in-plane uniaxial anisotropy has an energy between 40 and 200 kBT and wherein coercivity is larger than 200 Oe.
    Type: Grant
    Filed: May 2, 2020
    Date of Patent: July 5, 2022
    Assignees: Antaios, Centre National De La Recherche Scientifique
    Inventors: Witold Kula, Marc Drouard, Gilles Gaudin, Jean-Pierre Nozieres
  • Patent number: 11362266
    Abstract: A memory device may comprise a substrate defining a main plane; a plurality of memory cells each comprising a SOT current layer disposed in the main plane of the substrate and a magnetic tunnel junction residing on the SOT current layer; and a bit line and a source line to flow a write current in a write path including the SOT current layer of a selected memory cell. The source line comprises a conductive magnetic material providing a magnetic bias field extending to the magnetic tunnel junction of the selected memory cell for assisting the switching of the cell state when the write current is flowing.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: June 14, 2022
    Assignee: ANTAIOS
    Inventors: Marc Drouard, Jérémie Vigier, Jérémy Brun-Picard