Abstract: The present invention introduces a configurable register file architecture of a processing device (microprocessor, CPU, DSP) with multi-range shift register support. Said register file has two working modes which can be simultaneously active such that in addition to behaving as a conventional register file, said register file can also be configured such that the registers of said register file form one or more shift registers whose ranges are specified by dedicated ‘range control’ inputs of said register file. By incorporating the functionality of shift registers into the register file, register renaming is achieved at almost no hardware overhead, allowing furthermore a reduction in overall power consumption and machine code size.