Abstract: A method is disclosed of manufacturing a semiconductor structure comprising an (001) oriented zincblende structure group III-nitride layer, such as GaN. The layer is formed on a 3C-SiC layer on a silicon substrate. A nucleation layer is formed, recrystallized and then the zincblende structure group III-nitride layer is formed by MOVPE at temperature T3 in the range 750-1000° C., to a thickness of at least 0.5?. There is also disclosed a corresponding semiconductor structure comprising a zincblende structure group III-nitride layer which, when characterized by XRD, shows that the substantial majority, or all, of the layer is formed of zincblende structure group III-nitride in preference to wurtzite structure group III-nitride.

Abstract: A method is disclosed of manufacturing a semiconductor structure comprising an (001) oriented zincblende structure group III-nitride layer, such as GaN. The layer is formed on a 3C—SiC layer on a silicon substrate. A nucleation layer is formed, recrystallized and then the zincblende structure group III-nitride layer is formed by MOVPE at temperature T3 in the range 750-1000° C., to a thickness of at least 0.5 ?m. There is also disclosed a corresponding semiconductor structure comprising a zincblende structure group III-nitride layer which, when characterized by XRD, shows that the substantial majority, or all, of the layer is formed of zincblende structure group III-nitride in preference to wurtzite structure group III-nitride.

Abstract: We describe a method for reducing bow in a composite wafer comprising a silicon wafer and a silicon carbide layer grown on the silicon wafer. The method includes applying nitrogen atoms during the growth process of the silicon carbide layer on the silicon wafer so as to generate a compressive stress within the composite wafer.

Abstract: We disclose a high voltage semiconductor device comprising a semiconductor substrate of a second conductivity type; a semiconductor drift region of the second conductivity type disposed over the semiconductor substrate, the semiconductor substrate region having higher doping concentration than the drift region; a semiconductor region of a first conductivity type, opposite to the second conductivity type, formed on the surface of the device and within the semiconductor drift region, the semiconductor region having higher doping concentration than the drift region; and a lateral extension of the first conductivity type extending laterally from the semiconductor region into the drift region, the lateral extension being spaced from a surface of the device.

Abstract: A method comprises providing a monocrystalline silicon wafer (11) having a principal surface (17) which supports a masking layer (24), for example silicon dioxide or polycrystalline silicon, having windows (25) to expose corresponding regions of the silicon wafer, forming silicon carbide seed regions (30) on the exposed regions of the wafer, for example by forming carbon and converting the carbon into silicon carbide, and growing monocrystalline silicon carbide (31) on the silicon carbide seed regions. Thus, monocrystalline silicon carbide can be formed selectively on the silicon wafer which can help to avoid wafer bow.

Abstract: We disclose a semiconductor structure comprising a monocrystalline silicon wafer; spaced apart monocrystalline silicon carbide layers disposed directly on the silicon wafer; amorphous and/or polycrystalline silicon carbide layers disposed directly on the silicon wafer between the monocrystalline silicon carbide layers; first gallium nitride layers disposed on the monocrystalline silicon carbide layers; and second gallium nitride layers disposed on the amorphous and/or polycrystalline silicon carbide layers.

Abstract: A bipolar power semiconductor transistor is disclosed. The transistor includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type disposed on the semiconductor substrate; a semiconductor drift region of a second conductivity type, opposite the first conductivity type, disposed on the first semiconductor region, a body region of the first conductivity type located within the semiconductor drift region, a source region of the second conductivity type located within the body region, a gate placed above and in contact to the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region. The semiconductor substrate includes a material having silicon (Si) and the first semiconductor region includes a material having 3-step cubic silicon carbide (3C-SiC).

Abstract: A bipolar power semiconductor transistor is disclosed. The transistor includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type disposed on the semiconductor substrate; a semiconductor drift region of a second conductivity type, opposite the first conductivity type, disposed on the first semiconductor region, a body region of the first conductivity type located within the semiconductor drift region, a source region of the second conductivity type located within the body region, a gate placed above and in contact to the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region. The semiconductor substrate includes a material having silicon (Si) and the first semiconductor region includes a material having 3-step cubic silicon carbide (3C-SiC).