Abstract: A solder screen printing process comprises: providing a wafer having a plurality of chips thereon, and a passivation layer covering the chips while exposing a plurality of bonding pads of the chips, wherein the bonding pads have a plurality of under bump metal (UBM) structures formed thereon; forming a pattern layer on the wafer, wherein the pattern layer has a plurality of first openings that defines the locations on the chips where bumps are to be subsequently formed; providing a carrier that has a wafer mounting location, providing a mounting support means that is mounted on the carrier, wherein the mounting support means has a second opening of the wafer size, such that the wafer mounting location of the carrier is exposed through the second opening; mounting the wafer on the carrier through the second opening of the mounting support means; and filling the first openings with a solder paste.

Abstract: A wafer-level packaging process. A wafer having a plurality of bonding pads thereon exposed through a passivation layer formed on the wafer is provided, and an under bump metal (UBM) is formed on each bonding pad. A stress buffer layer is formed through which are formed a plurality of first openings that expose the under bump metals (UBM). Solder material is filled in the first openings of the stress buffer layer. Either a stencil or a patterned photoresist having a plurality of second openings is arranged on the stress buffer layer such that the second openings expose the first openings. A solder material is filled in the second openings. The solder material is reflowed, wherein if the stencil is used, it is removed before the reflow process while if the patterned photoresist is used, it is removed after the reflow process.

Abstract: A wafer-level packaging process comprising: forming a patterned photoresist on a wafer covering a plurality of scribe lines and bump forming locations; forming a stress buffer layer on the regions not covered by the patterned photoresist; after removal of the patterned photoresist a plurality of first openings are defined in the stress buffer layer that also exposes the scribe lines; arranging either a stencil or a second patterned photoresist having a plurality of second openings over the wafer to cover the stress buffer layer and scribe lines, such that the second openings expose the first openings; filling a solder material in the openings; performing a reflow process, wherein according to the use of either the stencil or second photoresist, the reflow is respectively performed after or before the removal thereof. After dicing, the thus-packaged wafer can be directly connected onto an external carrier.

Abstract: The present invention provides a leadframe package formed by flip chip on leadframe technique. The chips are face to face attached on both sides of the leadframe surface. Another embodiment according to the present invention is that the chips are back to back attached on a leadframe. A chip with smaller size is stacked on a further chip with larger size. The smaller chip is connected to the leadframe by wire bonding. The present invention includes a first chip attached on the leadframe by using flip chip technology. The first chip has a plurality of conductive bump for electrically transferring signal to external. The tape has a plurality of openings or slots through the tape. Each opening exposes the terminal of the inner leads. Thus, a further chip can be set on the opposite major surface of the leadframe by means of the openings or slots. The second chip can be optionally face to face formed on the other side of the leadframe or back to back stacked on the first chip.

Abstract: A testing means for holding chips to perform tests comprises of a plurality of inner leads for providing electrical connection for the chips with a plurality of conductive bumps. A metal layer is formed on surfaces of the plurality of inner leads for fixing the chips on the plurality of inner leads, wherein a melting point of the metal layer is below a melting point of the conductive bumps. Then, a adhesive material is pasted on a bottom surface of the plurality of inner leads for fixing the plurality of inner leads. A holding means is used to connect and hold the plurality of inner leads, and used for providing electrical connection for the plurality of inner leads.

Abstract: A packaging method for integrated circuit device, which is fit to apply flip chip bonding technique to a leadframe-type chip carrier. The packaging method will not increase the difficulty in assembly of the integrated circuit chip with the leadframe and is able to ensure that the integrated circuit chip be assembled with the lead fingers of the leadframe without false soldering. Also, the packaging method can achieve less inductance of the transmission line and faster transmission speed. In addition, the cost required of the packaging method can be much lower than that for the organic or ceramic base board.

Abstract: A hole is generated in a substrate. A chip is connected to the substrate by using the chip receiving area of the substrate by using flip chip assembly. The hole is aligned to the chip receiving area of the substrate. Then, a underfill process is performed such that the space between the chip and the substrate will be encapsulated using liquid capsulated material. The liquid capsulated material is injected into the hole from the back side surface of the substrate to the front side surface of the substrate.