Patents Assigned to Apex Design Systems, Inc.
  • Chip-area reduction and congestion alleviation by timing-and-routability-driven empty-space propagation
    Patent number: 7200827
    Abstract: An EDA (Electronic Design Automation) process which collects and moves empty-spaces among cells on a circuit layout to one or more target areas for productive use, such as chip-size reduction and routability congestion alleviation. The process includes globally moving the empty-spaces to the target area and thereafter locally moving the empty-spaces as refinement.
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: April 3, 2007
    Assignee: Apex Design Systems, Inc.
    Inventors: Tsu-Wei Ku, Wen-Chung Fang