Patents Assigned to Apex Microtechnology
  • Patent number: 10985713
    Abstract: Systems and methods are described for a power amplifier with a tracking power supply. The power amplifier may use envelope tracking. The power amplifier is protected when the output of the power amplifier is short circuited or overloaded.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: April 20, 2021
    Assignee: APEX MICROTECHNOLOGY, INC.
    Inventors: Gregory Michael Patchin, Miroslav Vasic, Vladan Lazarevic, Jens Eltze, Kirby Neil Gaulin, Jesus Angel Oliver, Pedro Alou, Jose Antonio Cobos
  • Patent number: 10957618
    Abstract: Disclosed herein are apparatuses and methods for configuring a circuit board to have a plurality of die having different bottom-side electrical potential. An apparatus comprises a circuit board comprising a metallic base plate, a thermally conductive dielectric, and a plurality of metallic pads. Each of a plurality of die of the apparatus is coupled to a respective one of the plurality of metallic pads, and the plurality of die comprises a first die and a second die. Based on each of the plurality of die being coupled to a respective one of the plurality of metallic foil pads, the first die is configured to exhibit a first bottom-side electrical potential and the second die is configured to exhibit a second bottom-side electrical potential. The apparatus is further configured to conduct heat from the plurality of die away from the plurality of die via at least the metallic base plate, the thermally conductive dielectric, and the plurality of metallic pads.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 23, 2021
    Assignee: Apex Microtechnology, Inc.
    Inventors: Kirby Gaulin, Emily Sataua, Alan Varner
  • Patent number: 9948242
    Abstract: A selectable current limiter circuit to limit the current an amplifier with a load. The limiter circuit limits the current of an amplifier by comparing a voltage reference that follows the output swing of the amplifier to voltage drop across a current limiting resistor coupled to the output of the amplifier. The limiter circuits are operatively coupled to buffer and switch circuits that delay the current limiting until the limiter circuits are activated.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: April 17, 2018
    Assignee: APEX MICROTECHNOLOGY, INC.
    Inventors: Alan Lee Varner, Gregory Michael Patchin, Kirby Neil Gaulin
  • Patent number: 9592665
    Abstract: A multiplexed multilevel converter amplifier. The converter is configured to generate a converter voltage. The converter voltage varies among a plurality of voltage levels. A multiplexer is comprised of at least four switches configured to generate a positive output voltage and a negative output voltage according to a configuration of the at least four switches. The positive output voltage varies between the converter voltage and a positive supply rail and the negative output voltage varies between the converter voltage and a negative supply rail. An amplifier is supplied by the multiplexer, and the amplifier generates an output voltage that varies between the positive output voltage and the negative output voltage. A control module is configured to control the configuration of the at least four switches of the multiplexer and the plurality of voltage levels of the converter voltage, such that the converter voltage is synchronized with the output voltage.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: March 14, 2017
    Assignee: APEX MICROTECHNOLOGY, INC.
    Inventors: Miroslav Vasic, Oscar Garcia, Pedro Alou, Jesus Oliver, José A. Cobos, Eric J. Boere
  • Patent number: 7339433
    Abstract: A differential amplifier stage includes one active load circuit connected to a pair of cross-coupled transistors that produce a differential signal. The active load circuit controls the rise time of the differential signal. The differential amplifier stage also includes another active load circuit connected to the pair of cross-coupled transistors. The second active load circuit controls the fall time of the differential signal.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: March 4, 2008
    Assignee: Apex Microtechnology Corporation
    Inventors: Anindya Bhatacharya, David F. Cox
  • Patent number: 7292087
    Abstract: An apparatus includes an integrated circuit that includes low side power supply circuitry that provides an output voltage for H-bridge circuitry. The low side power supply circuitry includes one transistor that provides one current to the output of the low side power supply circuitry in response to the output voltage of the low side power supply circuitry dropping below a quiescent level. The low side power supply circuitry also includes a second transistor that controls the conduction state of a third transistor, based at least in part, upon the first transistor providing the first current to the output of the low side power supply circuitry. The third transistor provides a second current to the output of the low side power supply circuitry.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: November 6, 2007
    Assignee: Apex Microtechnology Corporation
    Inventor: Arthur M. Cappon
  • Patent number: 6496068
    Abstract: An amplifier circuit that includes an amplifier stage and an output stage, and local feedback between these stages to drive a biasing string associated with the amplifier stage using the potential at the output stage. In one embodiment, the local feedback line is coupled between the output stage and the biasing string to remove the loading effect of the biasing string on the amplifier stage. In another embodiment, the local feedback line is coupled between the switches of the amplifier stage and the switches of the output stage to bias the amplifier stage using the output stage.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: December 17, 2002
    Assignee: Apex Microtechnology Corporation
    Inventor: Dennis Eddlemon
  • Patent number: 5519357
    Abstract: A biasing arrangement for a quasi-complementary output stage having first and second transistors of a first type, where at least one of the transistors is driven by a third transistor of a second type. The inventive biasing arrangement comprises a first circuit for biasing the third transistor and a second circuit having a third circuit for providing an input signal to the first transistor and a fourth circuit for providing the input signal to the first circuit. In a particular implementation, the first circuit is connected between the input terminals of the first and the third transistors. The third circuit is a fourth transistor having a first terminal connected to a first source of supply, a second terminal connected to a source of the input signal and a third terminal connected to a second source of supply. The third terminal of the fourth transistor is connected to the second source of supply via a first resistor.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: May 21, 1996
    Assignee: Apex Microtechnology
    Inventor: Dennis N. Eddlemon
  • Patent number: 5365194
    Abstract: An improved power operational amplifier device is disclosed which provides a floating buffer having a first and second RC time constant for controlling a first bank of MOSFET transistors in an output portion of the device. In addition, the power operational amplifier includes a fixed buffer having a third RC time constant for controlling a second bank of MOSFET transistors located in an output portion of the device. A current limit section is coupled to both the floating buffer and the fixed buffer, and, in addition, the current limit section of the improved power operational amplifier has an oscillation stabilizer portion for limiting oscillations of output current during output stage current limit operation. The device also includes an output portion coupled to each of the floating buffer, the fixed buffer, and the current limit section.
    Type: Grant
    Filed: June 3, 1993
    Date of Patent: November 15, 1994
    Assignee: APEX Microtechnology Corporation
    Inventor: William K. Sands, Jr.
  • Patent number: 5210505
    Abstract: An operational amplifier input stage includes two transistors coupled as a differential amplifier to receive input signals. At least one transistor is stacked in a load circuit of each input transistor for the purpose of lowering the voltage across each transistor. In order to eliminate the effects of error currents resulting from conventional resistor self biasing of the stacked transistors, two nodes, to which the input transistors are coupled, are identified. According to a first embodiment, feedback circuits are coupled to each node and each feedback circuit maintains the coupled node at a voltage level established by the feedback apparatus of the operational amplifier. According to a second embodiment, a single feedback circuit controls the voltage at a first node and the same feedback circuit maintains the voltage level of a second node at a constant level.
    Type: Grant
    Filed: March 10, 1992
    Date of Patent: May 11, 1993
    Assignee: Apex Microtechnology Corporation
    Inventor: Dennis N. Eddlemon
  • Patent number: 5142243
    Abstract: An operational amplifier input stage includes two transistors coupled as a differential amplifier to receive input signals. At least one transistor is stacked in a load circuit of each input transistor for the purpose of lowering the voltage across each transistor. In order to eliminate the effects of error currents resulting from conventional resistor self biasing of the stacked transistors, two nodes, to which the input transistors are coupled, are identified. A feedback circuit is coupled to each node and each feedback circuit maintains the coupled node at a voltage level established by the feedback apparatus of the operational amplifier. The disclosed circuit eliminates circuit drift and offset voltages resulting from changes in common mode and/or power supply voltages by eliminating the effects of resistive loading on the input stage components.
    Type: Grant
    Filed: December 19, 1990
    Date of Patent: August 25, 1992
    Assignee: Apex Microtechnology Corporation
    Inventor: Dennis N. Eddlemon
  • Patent number: 4871965
    Abstract: An environmental testing facility for verifying operational conditions of electronic components at predefined temperature extremes is described. A removable multistation holder is configured to have a plurality of components coupled thereto. The multistation holder is coupled to a controllable, rotatable shaft. A hood is placed over the holder, shaft and associated apparatus and placed in contact with a base plate, so that a vacuum can be established in the resulting chamber. A sensing device permits the positioning of the individual components with respect to an interface apparatus. When the component is correctly positioned with respect to the interface apparatus, the interface apparatus is moved to engage the terminals of the components. The electrical signals can be applied to and received from the component through the interface device. After a first temperature condition is established for the multistation holder and consequently for the components coupled thereto, all of the components are tested.
    Type: Grant
    Filed: August 18, 1988
    Date of Patent: October 3, 1989
    Assignee: Apex Microtechnology Corporation
    Inventors: Hubert F. Elbert, Gary March-Force
  • Patent number: 4833423
    Abstract: In a wide-band direct-coupled transistor amplifier, the current through the power output stage must be stabilized to prevent fluctuations in the amplifier output signal. To stabilize the output stage current, a negative feedback loop is established providing a bias control for the amplifier input stage. In the past, voltage feedback apparatus, typically including operational amplifiers, has been utilized. In the present invention, a current feedback path, which avoids the voltage level translation inherent in the prior art, is used to provide the feedback bias control for the input stage of the amplifier. A technique for the compensation of temperature drift and for voltage offset is described.
    Type: Grant
    Filed: July 20, 1987
    Date of Patent: May 23, 1989
    Assignee: Apex Microtechnology Corporation
    Inventor: John J. Molloy
  • Patent number: 4808909
    Abstract: A circuit for providing a constant current and a constant bias voltage is described. The circuit includes two paths coupled between a positive voltage supply +V.sub.S and a negative voltage supply -V.sub.S. Each path inlcudes a Zener diode and a enhancement mode field effect transistor (FET) device (the FET device being coupled in a diode configuration) which are connected in series. Each path of the circuit further includes an FET device and an associated resistor combination, coupled in series with the Zener diode and the diode-coupled FET device. The FET device and the associated resistor function as a current source component. A gate terminal of each FET device of the current source component is coupled across the Zener diode and the diode-coupled FET device of the other circuit path.
    Type: Grant
    Filed: October 15, 1987
    Date of Patent: February 28, 1989
    Assignee: Apex Microtechnology Corporation
    Inventor: Dennis N. Eddlemon