Abstract: A biasing arrangement for a quasi-complementary output stage having first and second transistors of a first type, where at least one of the transistors is driven by a third transistor of a second type. The inventive biasing arrangement comprises a first circuit for biasing the third transistor and a second circuit having a third circuit for providing an input signal to the first transistor and a fourth circuit for providing the input signal to the first circuit. In a particular implementation, the first circuit is connected between the input terminals of the first and the third transistors. The third circuit is a fourth transistor having a first terminal connected to a first source of supply, a second terminal connected to a source of the input signal and a third terminal connected to a second source of supply. The third terminal of the fourth transistor is connected to the second source of supply via a first resistor.