Abstract: Techniques improve integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through statistical analysis. A design management component (DMC) can determine a trained model representing timing path properties and operating conditions of agnostic timing paths based on an analysis of vectorized data that represents timing path information associated with the agnostic timing paths. DMC can perform statistical regression on the vectorized data to facilitate training the trained model. A static timing analysis (STA) component can perform STA on design information associated with the integrated circuitry design and determine an operating condition of a timing path of the integrated circuitry design based on the STA. DMC can predict or determine at least one other operating condition associated with the integrated circuitry design based on the operating condition and the trained model.

Abstract: Techniques improve integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through spice-based timing path labeling and statistical analysis. Design management component (DMC) can randomly determine and generate sample timing paths based on parameters of characteristics associated with the sample timing paths, the parameters determined based on random seed values; simulate responses of the sample timing paths; and generate vectorized data based on the simulated responses. DMC determines a trained model representing timing path properties and operating conditions of sample timing paths based on statistical analysis of vectorized data. Static timing analysis (STA) component can perform STA on design information of integrated circuitry design and determine an operating condition of a timing path of the design based on the STA.

Abstract: A corner prediction system applies data generated through discrete process, voltage, and temperature (PVT) corner prediction to achieve highly accurate continuous corner prediction coverage. Embodiments of the corner prediction system can be trained to generate accurate performance metric prediction for a continuous range of PVT corners within a design space given a set of available pre-trained PVT corners. The corner prediction system can address the need to provide accurate continuous timing prediction coverage of design operating conditions (represented by PVT corners) through the availability of discrete PVT corners.

Abstract: A flexible standards-based bridge or switch chiplet facilitates heterogeneous integration of chiplets that support different physical layer (PHY) interfaces and communication protocols. The bridge chiplet is configured with multiple PHY interfaces and associated adapter logic and translation logic for translation between different PHY interfaces and protocols. The bridge chiplet can be programmed to serve as a die-to-die interconnect bridge that routes data between multiple chiplets supporting different PHYs and interconnect protocols. Some embodiments of the bridge chiplet can serve solely as a PHY bridge, while others may serve as a bridge for both PHYs and protocols.

Abstract: Techniques improve integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through spice-based timing path labeling and statistical analysis. Design management component (DMC) can randomly determine and generate sample timing paths based on parameters of characteristics associated with the sample timing paths, the parameters determined based on random seed values; simulate responses of the sample timing paths; and generate vectorized data based on the simulated responses. DMC determines a trained model representing timing path properties and operating conditions of sample timing paths based on statistical analysis of vectorized data. Static timing analysis (STA) component can perform STA on design information of integrated circuitry design and determine an operating condition of a timing path of the design based on the STA.

Abstract: A new DRAM architecture, HPPC DRAM, is provided to support a high performance and low cost memory system. The HPPC DRAM has integrated the following concepts into a single DRAM chip. First, superset pin definitions backward-compatible to the traditional fast-page-mode DRAM SIMM. This allows one memory controller to support a memory system having both a traditional fast-page-mode DRAM and HPPC DRAM of this invention. Secondly, combining a memory array, a register of 4:1 Mux/Demux function, a RAS buffer/decoder, a CAS buffer/decoder, a burst address counter, a page register/comparator, a sequencer and a data buffer into a single DRAM IC chip. Using these intelligent peripheral circuits, the HPPC DRAM execute a pipeline cycle request and precharge cycle stealing. Thirdly, a precharge cycle stealing pipeline is implemented to the timing chain of read operation to eliminate the precharge cycle time which is achieved by executing read drive concurrently to the precharge cycle.