Abstract: A flash memory device having a low threshold voltage distribution is disclosed. The threshold voltage in a program state of a flash memory cell is defined to be near or slightly greater than approximately 3.0 volts. The threshold voltage in an erased state is defined to be less than 0.7 volts or at ground level. The low threshold voltage distribution makes it possible to use a low voltage around 3.0 volts for the gate of the memory cell in a read operation. The UV erased threshold is raised to near the threshold voltage of a program state to avoid data retention problem.

Abstract: A flash memory circuit includes a word line decoder with even and odd word line latches and a source line decoder with a source line latch. The word line decoders and the source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that may be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments and having segmented source lines controlled by source segment control lines and transistors, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.

Abstract: Flash memory circuits provide sector protection or file protection with protection attribute status bits held in a flash memory array. The sector protection protects memory data based on the physical location of the data. The flash memory array is divided into a number of memory sectors. Each memory sector can be protected independently. The size of the memory sector is flexible and may be as large as the whole memory array or as small as a single bit group. Each memory sector has protection bits stored in a protection bit array for indicating the protection state of the sector. A parallel protection structure providing both sector protection and block protection is also included. The parallel protection allows small size data protection as well as large size block protection. File protection protects memory data on a file basis regardless of the physical location of the data. Each file has protection bits stored in an attribute memory for indicating the protection state of the file.

Abstract: A pure MOS-implementable oscillator requires no trimming to make the oscillation frequency Vdd independent, but permits trimming to compensate for process and fabrication variations. A current generator creates a core reference current Iosc0, mirrored programmable trim currents, and dynamic reference voltages that do not require a constant Vdd source. A programmable delay unit provides value-programmable capacitors that receive mirrored currents A.times.(M/N).times.Iosc0, where A is a MOS channel W/L ratio constant, and M and N are integers. The currents create ramp-like voltage signals across the capacitors, the slewrate being A.times.(M/N).times.Iosc0/capacitance. A comparator unit compares the ramp-like signals, which ramp-down from Vdd, against a (Vdd-Vt) reference voltage (Vt being a MOS threshold voltage). The comparator unit outputs complementary signals that toggle a set-reset flipflop, whose output is the oscillator output signal.

Abstract: A flash memory circuit having a word line decoder with even and odd word line latches and a source line decoder with a source line latch is disclosed. The word line decoders and source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.

Abstract: The invention provides a flash memory and decoder with overerase repair that can provide three word line voltages to overcome the overerased problems. The wordline decoder includes a wordline latch that provides a high flexibility of erasing size so that single/multiple sub-wordlines, single/multiple wordlines, single/multiple block, and whole array can be erased simultaneously. An exemplary embodiment of a flash memory wordline decoder that can provide three voltages includes a plurality of voltage terminals to receive a plurality of voltages, a plurality of address terminals to receive a plurality of address signals, a procedure terminal to receive a procedure signal, and a plurality of output wordlines adapted to be coupled to a bank of flash transistors.

Abstract: A flash memory with a flexible erasing size includes a first bank of flash transistors and a second bank of flash transistors. Each bank of flash transistors forms a plurality of rows and a plurality of columns, each transistor having a gate, drain and source, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the first bank are all coupled to a first sourceline and the sources of the transistors in the second bank are all coupled to a second sourceline. A wordline decoder is coupled to the wordlines and configured to receive a wordline address signal and to decode the wordline address signal to select a wordline, where the wordline decoder includes a wordline latch configured to latch the selected wordline.

Abstract: A flash memory circuit having a word line decoder with even and odd word line latches and a source line decoder with a source line latch is disclosed. The word line decoders and source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminates over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.

Abstract: A flash memory includes a flash transistor array, a wordline decoder, a bitline decoder, a sourceline decoder and a read/write controller. The read/write controller has a voltage terminal to receive an input voltage and a data terminal to receive a new data signal. A sense amplifier is coupled to the bitline decoder and configured to sense a signal on a selected bitline and to generate an internal old data signal. A data comparator is coupled to the data terminal and the sense amplifier and configured to compare the new data signal to the old data signal and to generate a comparator signal. A voltage generator is configured to selectively apply one of a read set of voltages to read a selected cell in the flash transistor array, a program set of voltages to program a selected cell and an erase set of voltages to erase a selected cell. In a multistate embodiment, the read/write controller further includes a step counter configured to generate a plurality of step counts.

Abstract: The invention provides a flash memory with row redundancy. The memory includes an input terminal to receive an address and a command signal. A plurality of flash memory arrays are arranged as blocks, where each block includes a plurality of transistors organized in rows and columns and having respective wordlines, bitlines and a sourceline. A wordline decoder is coupled to the input terminal and a portion of the plurality of blocks and configured to decode a portion of the address and to receive a control signal to selectively apply a predetermined voltage to a wordline. A bitline decoder is coupled to the input terminal and to the plurality of blocks and configured to decode a portion of the address and to selectively pass a predetermined bitline to an output terminal. A match circuit is coupled to the input terminal and to a portion of the plurality of blocks and configured to decode a portion of the address and to receive the control signal to selectively apply a predetermined voltage to a wordline.

Abstract: In a method and circuit for refreshing a flash memory with a memory array, data corresponding to that stored in a memory cell of the memory array is read by applying a read voltage thereto. Thereafter, an erase verify voltage lower than the read voltage is applied to the memory array, and conduction of the memory cell is sensed. Based on non-conduction of the memory cell and the data of the memory cell, the memory cell is selectively discharged to compensate for undesired charge gain. Subsequently, a program verify voltage higher than the read voltage is applied to the memory array, and conduction of the memory cell is sensed. Based on conduction of the memory cell and the data of the memory cell, the memory cell is selectively charged to compensate for undesired charge loss. A method and circuit for initiating the refresh operation automatically is also disclosed.

Abstract: A memory device with an on-chip manufacturing and memory cell defect detection capability includes a memory array with a plurality of memory cells that are organized in rows and columns, a plurality of word lines that interconnect respectively the rows of memory cells, and a plurality of bit lines that interconnect respectively the columns of memory cells. Global word line short and global word line open testing circuits are provided to detect the presence of a word line short or word line open condition. Local word line short and local word line open testing circuits are provided to identify the defective word line. Global bit line short and global bit line open testing circuits are provided to detect the presence of a bit line short or bit line open condition. A local bit line short/open testing circuit is used to identify the defective bit line.

Abstract: A memory cell array of a flash electrically erasable programmable read only memory (EEPROM) includes a plurality of transistor cells arranged in rows and columns. The sources of transistor cells in the same memory block are connected to a main source line through a control gate, as are the drains. The separate source and drains in the column direction are designed for a bit-based write capability. Writing, such as erasing or programming, of a selected transistor cell uses the Fowler-Nordheim tunneling method and can be accomplished due to the programming or erase inhibit voltage that is applied to non-selected transistor cells. The associated circuitry for bit-based writing, as well as methods of programming and erasing the memory cell array, with over-program and over-erase repair capability, are also disclosed.

Abstract: A flash memory wordline decoder includes a plurality of voltage terminals to receive a plurality of voltages, a plurality of address terminals to receive a plurality of address signals, a procedure terminal to receive a procedure signal, and a plurality of output wordlines adapted to be coupled to a bank of flash transistors. The wordline decoder circuit is configured to decode the address signals and includes latches coupled to the wordlines, where the latches are configured to latch the wordlines and to provide an operational voltage on the wordline to accomplish a predetermined operation responsive to the procedure signal. Advantages of the invention include a verification with a low verification voltage such as 1 V or less for operating with a VDD supply voltage as low as 1.5 V. The decoder also reduces erase/write cycle time and improves expected lifetime of the flash memory due to reduced stress on the flash transistors within the flash memory.

Abstract: A flash memory includes a bank of flash transistors forming a plurality of rows and a plurality of columns, each flash transistor having a gate, drain and source, where the gates of flash transistors in each row are coupled to common wordlines, the drains of flash transistors in each column are coupled to common metal 1 lines divided into even metal 1 lines and odd metal 1 lines and the sources of the flash transistors are coupled to a common sourceline. A set of first selection transistors are coupled between even metal 1 lines and metal 2 lines having a pitch twice that of said metal 1 lines and controlled by a first select signal to selectively couple the even metal 1 lines to the metal 2 lines. A set of second selection transistors are coupled between odd metal 1 lines and the metal 2 lines and controlled by a second select signal to selectively couple the odd metal 1 lines to the metal 2 lines.

Abstract: A flexible word-erase flash memory includes a first bank of flash transistors forming a plurality of rows and a plurality of columns, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the first bank are all coupled to a first sourceline. A second bank of flash transistors form a plurality of rows and a plurality of columns, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the second bank are all coupled to a second sourceline. A wordline decoder is coupled to the wordlines and configured to receive a wordline address signal and to decode the wordline address signal to select a wordline.

Abstract: A flat-cell ROM array includes a bank of field effect transistors, each having a source, drain and gate, formed by ion implantation between columns of buried N+ and under rows of polysilicon, wherein adjacent columns of buried N+ are the source and drain of at least one transistor and a corresponding row of polysilicon is the gate of the transistor. Each of these transistors is programmed to have one of a plurality of threshold voltages depending on a desired storage value. Attached to the bank of transistors is an upper selector network associated with the bank connected to a first class of alternating sets of the columns, and a lower selector network associated with the bank connected to a second class of alternating sets of the columns. A method provides steps for performing the present invention.

Abstract: A multistate PROM and decompressor comprises a PROM array including a plurality of cells arranged to have a plurality of wordlines and a plurality of bitlines, where each cell is configured to have one of a plurality of threshold voltages (Vt0-Vtn). A Vt-detector is coupled to the PROM array and configured to receive a high voltage wordline (WLHV) signal that is ramped from a first voltage (e.g. 0V or ground) to a second voltage (e.g. Vtmax). The Vt-detector is configured to compare the WLHV signal to a plurality of predetermined thresholds and to output a detector word in response to the WLHV signal. An addressed memory cell is selected by a wordline select signal and a bitline select signal. A wordline selector is coupled to the PROM array and configured to receive the WLHV signal. The wordline selector communicates the WLHV signal to a selected wordline in response to the wordline select signal.