Abstract: A system for the management of computer programs in a computer network environment is presented. A network license server comprises a license server daemon which provides access to a computer program based on information stored in user and license databases. To track software usage, the daemon also maintains a log file which can be accessed by and interfaced with a network administration station. The network license server protects software vendors from unauthorized use of their software while permitting software programs and users to reside anywhere on the network.

Abstract: A method and apparatus is disclosed for improving the performance of a digital computer by reducing the latency of read operations and increasing available write bandwidth by utilizing a subset of the address bits which are the same from one operation to the next. A faster cycle type (e.g. page mode or static column) can thereby be employed in the Dynamic Random Access Memory (DRAM) memory by eliminating the DRAM precharge and RAS address portions of the cycle.

Abstract: A clock generation circuit on each circuit board of a computer system and which removes board-to-board system skew in clock signal distribution. A phase-locked loop is employed to maintain synchronization between the system reference clock signal distributed to each board and the outputs of the distribution gate array in the generation circuit on each board. A 2X frequency clock is provided by combining the clock signal with a delayed version of itself. A second order loop is employed to monitor the duty cycle of the 2X frequency clock and to adjust the duty cycle of the regular frequency clock to provide cycle-to-cycle symmetry for the 2X frequency clock.

Abstract: A method and apparatus for selectively filling a cache memory with a variable number of data words in response to the size and type of data transfer requested by the processor associated with the cache. According to the present invention a cache fill of either 16 or 64 bytes are provided. If there is a cache miss and an 8 byte word data transfer as requested, the larger fill is provided, similarly, if the 8 byte word data transfer is not requested, the shorter block of data is provided, resulting in enhanced performance over a fixed length cache fill.

Abstract: A decentralized, pipelined, synchronous bus arbitration scheme which allows almost completely fair arbitration between multiple devices competing for the use of a communication bus while allowing the device that last used the bus faster access to the bus if no other device is competing for its use. The arbitration method and apparatus according to the present invention allows all competing devices equal access to the bus, with the exception that when bus requests are posted simultaneously, the device with the higher priority will always be granted use of the bus first.

Abstract: A software configuration management system that uses a network computing environment to build large software systems in parallel. A configuration manager assigns the compilation of buildable components of a software system to different processors in the network. Buildable components are assigned in order, according to dependencies between components, independent components taking precedence. Processors are chosen according to the amount of idle time during a sampled time segment. A display provides processor compilation status messages for each compilation discrete from status messages of other compilations. A continuously updated overall status report of the system being built is simultaneously displayed with, but segregated from, the compilation status messages.

Abstract: An AC to DC converter comprises a bridge rectifier followed by a boost circuit. The boost circuit includes an inductor, diode and load capacitor in series and a shunting switch connected to shunt the diode and load capacitor. The control circuit for switching the shunting switch comprises a differential circuit, a multiplier and a duty cycle generator in a feedback loop which maintains a constant output voltage on the capacitor. To eliminate the response to ripple on the output voltage, the differential circuit does not respond to voltages within a dead band.

Abstract: A processing system for controlling a computer graphics display stores and processes bit-mapped digital pixel values to generate color display signals. The system incorporates memory elements for storing control values for each pixel, in association with color values for each pixel. Processing modules responsive to the per-pixel control and color values generate color display signals. Embedding per-pixel control information in the bitmap in association with per-pixel color information enables each pixel to independently control the operation of the processing modules on that pixel.

Abstract: A support system for Computer-Aided Software Engineer (CASE) applications provides configuration management and features such as transparent retrieval of named versions of program sequences on a line by line basis as well as task monitoring and reporting. A modification record is maintained for all changes to the modules in the system build library by version numbers. Any version of a module can be obtained on a line by line basis as well as several different versions simultaneously thus supporting multiple concurrent system work on different versions by multiple users. Module monitoring is provided whereby if a module is modified when it is being monitored, all persons who might be affected thereby are notified. Task monitoring also provides notification and monitoring of tasks being accomplished as well as "blueprints" to follow in the future for the accomplishment of the same or similar tasks.

Abstract: In a display system for a data processing system color words for display at sequential pixels are obtained by addressing a lookup table memory with addresses obtained from a bit map display memory. Initialization data is stored in the display memory and, during an initialization procedure, is applied to the lookup table along the same data path used by the addresses during display. In one system a multiplexer takes the form of a shift register into which sequential pixel addresses are applied in parallel to interleaved stages. The two LUT addresses are read out sequentially by shifting the shift register. During the initialization procedure shifting is disabled and the interleaved address and data bytes are applied along separate address and data lines to the lookup table. One data path can be utilized for either eight plane or four plane display.

Abstract: Wall mounted connectors are provided in a communications ring network. The connectors join signal carrying lines until a communications node is connected into the network at the connector. When a plug from the node is inserted into the connector socket and rotated, plug contacts on the node plug are brought into contact with fixed, line contacts within the connector. Also, an electrical path through line closing conductors in the connector is broken. When the plug is rotated back and removed from the connector, the ring is again completed through the line closing conductors. The line closing conductors are mounted to a wheel which is driven by the plug. The rotor is positioned within a shielded enclosure formed by two pairs of upper and lower plates connected to the outer conductors of respective coaxial signal lines. A pawl pivoted on a biasing wheel drives the wheel back to the nonrotated position unless the wheel is rotated through half of a full rotation.

Abstract: In a ring communication system, data is received by and retransmitted by a plurality of network interface units spaced along the ring. Each network interface unit includes an elastic storage buffer which is preferably less than two bits in length. A feedback loop in each unit continuously controls the data transmitting rate from the network interface unit as a function of the average number of data bits in the elastic storage buffer. By thus controlling the transmitting rate, delay of data in the elastic storage buffer is controlled. Each network interface unit provides some of the delay required to cause the sum of all delays in the ring to become a multiple of 360 degrees. The entire network thus stabilizes at a substantially common frequency which provides the necessary phase delays throughout the network to provide a total phase shift of a multiple of 360 degrees.