Abstract: In a computer system having two processors both of which are used to process frames, a method for synchronizing a first set of frames corresponding to the first processor with a second set of frames corresponding to the second processor. A value stored in a register is initialized at frame boundaries of the second set of frames. This register value is repeatedly incremented during the frames of the second set of frames so that it increases within the frames. The value in the register is read. A timer value which provides a timing reference for each frame of the first set of frames is read. The value stored in the register when a frame boundary of the second set of frames had occurred is computed, based on the read register value and the read timing value. Based on the computed values, a frame length of the first set of frames is adjusted to maintain or improve frame synchronization between the two frame sets. Furthermore, data synchronization is provided in a similar fashion.

Abstract: A memory management unit (MMU) for controlling a CPU's right to access a memory in order to initiate performance of an operation. The MMU includes a translator for translating a virtual address issued by the CPU into a physical address, a domain number and a permission, and an environment controller for determining if a portion of the memory corresponding to the domain number can be accessed by the CPU. The translator includes a translation look-aside buffer (TLB) for generating the physical address, the domain number and the permission, provided an entry in a translation table of the TLB matches a page number component of the virtual address. The translator also includes translation table look-up logic which supplies entry information to the translation table of the TLB by finding a match for the page number component in the memory if a match cannot be found in the TLB.

Abstract: A computer system for manipulating notes on a screen of a computer display is provided. Each note area may include graphical, text, and data objects. An initial note area is provided with a header bar which includes the date of creation, the note number, and/or other indicia. When a user desires to make a new note, a division gesture is made on the computer display by moving a stylus horizontally across the screen. Once a division gesture is detected, the height of the preceding note is determined, and the height of the new note is considered to be indefinite or infinite. Each new division gesture creates a new header bar for the new note indicating the date of creation, the note number, and/or other pertinent information.

Abstract: Briefly, a method and apparatus for mixing a plurality of channels of digital audio samples using a non-linear clipping function which has a variable scaling factor is disclosed. The non-linear curving function is capable of being graphically represented by a curve which is sloped at the edges before reaching the maximum values. In a first embodiment, the non-linear clipping function is applied to the samples and values are calculated in real-time. Preferably, inputs to the non-linear clipping function are modified depending upon any significant trends, e.g. increasing or decreasing, in the sums of samples over time. In a second embodiment, to reduce processor overhead, prior to real time application of the non-linear clipping function, the calculations are performed and a lookup table is generated. This lookup table is then used during real time to apply the clipping function to the input data so that the non-linear function is not recalculated whenever multiple channels are mixed.

Abstract: A method for automated preparation of a formal communication, in a format such as a facsimile transmission, a letter or a memorandum, from an text object, a graphics object or a general object received by a computer system. The computer system examines the object information and determines (1) the desired format for the communication and (2) the information to be included in the body or substance of the communication. A given format, such as a facsimile transmission, has a corresponding template and a set of associated information queries to be answered to "fill in" the template information items. The computer system determines as many answers as possible for the information queries by examining the object. Any unanswered queries may be answered by the writer or supplier of the object. The computer system then prepares the body of the communication, including identification of people, geographical locations, events, times and dates referred to in the object.

Abstract: A device and method are provided for mapping address bus bits to memory address by using interleaved and non-interleaved modes so that every desired row and column configuration stored in a register file may be supported. Also, the device and method allow a combination of interleaved and non-interleaved memory bank pairs to be used by registering row and column address in a plurality of registers corresponding to interleaved and non-interleaved combinations. In particular, the memory bank pairs which are capable of being interleaved have the interleaved operation performed automatically while the memory bank pairs which cannot be interleaved have the non-interleaved operation performed thereon. As a result, the performance of the memory is enhanced while eliminating the amount of user interface necessary.

Abstract: An enclosure with a horizontal axis of rotation near the base of the enclosure, plus an adjustable foot to form a three-point support. The adjustable foot can be moved in a circle around a horizontal axis of rotation, thereby providing a range of stable positions. The adjustment mechanism includes a detent and matching depressions to allow certain fixed adjustments which will not slip.

Abstract: A hierarchical Z-buffer scan-conversion algorithm that does well on both (a) quickly rejecting most of the hidden geometry in a model, and (b) exploiting the spatial and temporal coherence of the images being generated. The method uses two hierarchical data structures, an object-space octree and an image-space Z-pyramid, in order to accelerate scan conversion. The two hierarchical data structures make it possible to reject hidden geometry very rapidly while rendering visible geometry with the speed of scan conversion. For animation purposes, the algorithm is also able to exploit temporal coherence. The resulting method is well suited to models with high depth complexity, achieving significant speedup in some cases compared to ordinary scan conversion.

Abstract: A node for a communication system that has a plurality of nodes, each of which may be coupled to a local host. The nodes are coupled between themselves in a tree topology by a plurality of point-to-point links. The interconnected nodes provide a first bus configuration for arbitration like a single bus. Following arbitration, the interconnected nodes provide a second configuration for high speed unidirectional data transfer without the bandwidth limitations of a single bus. Each node includes an arbiter, a data bus, a plurality of ports, a first multiplexer to select either the arbiter or the data bus, and a second multiplexer to select either the arbiter or the data bus. The data bus includes a transmit bus and a receive bus that are coupled with a repeater circuit that can resynchronize the data. During arbitration, the multiplexers select the arbiter to provide the function of a single bus for all the nodes. During data transfer, the multiplexers are configured for transmission of data.

Abstract: A handwriting signal processing front-end method and apparatus for a handwriting training and recognition system which includes non-uniform segmentation and feature extraction in combination with multiple vector quantization. In a training phase, digitized handwriting samples are partitioned into segments of unequal length. Features are extracted from the segments and are grouped to form feature vectors for each segment. Groups of adjacent from feature vectors are then combined to form input frames. Feature-specific vectors are formed by grouping features of the same type from each of the feature vectors within a frame. Multiple vector quantization is then performed on each feature-specific vector to statistically model the distributions of the vectors for each feature by identifying clusters of the vectors and determining the mean locations of the vectors in the clusters. Each mean location is represented by a codebook symbol and this information is stored in a codebook for each feature.

Abstract: A computer system having a processor and a coprocessor, a method and apparatus for developing and executing tasks on a coprocessor. A teamwork operating system for utilizing the coprocessor, e.g. a digital signal processor, resides in part on the processor and in part on the coprocessor. Such a teamwork operating system provides for optimum throughput of work through the coprocessor. An Application Programming Interface (API) is provided to facilitate the development of host application programs that will utilize the coprocessor. A Task Programming Interface (TPI) and a Task Unit Definition Language (TUDL) are provided to facilitate the development of coprocessor code for execution on the coprocessor.

Abstract: A protocol for transferring audio data and control/status data between audio functional units. The protocol involves multiplexing the audio data and control/status data. The multiplexed data is then transferred between a first audio unit and a second audio unit on two wires, each corresponding to the direction of data flow, and according to a clock and a synchronization pattern on third and fourth wires respectively.

Abstract: An apparatus and method for emulation routine pointer prefetch are disclosed. The apparatus includes an emulated program counter (EPC), a prefetch state machine, a summing device, an opcode storage device, and a pointer storage device. The EPC, opcode storage device and pointer storage device are coupled to a bus to receive, store and output an emulated program counter value, an opcode value and a pointer to a next emulation routine. The EPC, opcode storage device, and pointer storage device are controlled by the prefetch state machine, which also is coupled to the bus to detect a reference to a reserved memory address and stores an updated emulated program counter value in the EPC using the summing device. The prefetch state machine uses the EPC value to prefetch the next source instruction to be emulated in a first memory operation. A portion of the prefetched source instruction is the opcode value and is stored in the opcode storage device.

Abstract: A system for decoding guest instructions includes an emulation routine store in host processor addressable memory having a set of emulation programs beginning at corresponding emulation program addresses. A sequence of guest instructions is stored in the host processor addressable memory, and logic is provided which retrieves a current guest instruction in the sequence and jumps directly to an emulation program address in response to the current guest instruction. The emulation routine store is optimized by dividing it into a dispatch table having a set of dispatch entries and an emulation routine store storing a set of emulation entries. Each dispatch entry includes a plurality of host instructions of the emulation program corresponding to a particular guest instruction. The plurality of host instructions in a dispatch entry includes a host jump instruction which causes a jump to an emulation entry.

Abstract: In a computer including at least one caller adapted to request access to a storage media, the storage media being organized according to one of at least one file system format, a system for handling requests for access to the storage media.

Abstract: A signal distribution system having a converter with input terminals for receiving signals of varying configurations and an output terminal for transmitting converted signals. The input signals received by the converter are each converted into a converted signal frequency component of a common bus signal, which is then transmitted by the converter. The converter output terminal transmits the common bus signal on a communication bus. The communication bus is coupled to at least one interface pod for receiving the common bus signal and re-transmitting a desired converted signal.

Abstract: A galvanic isolation device having a light-emitting diode and a photo-transistor. A control circuit, which is coupled to the light-emitting diode and which controls the light-emitting diode, is provided. A signal generator circuit, which is coupled to the photo-transistor, is also provided. The signal generator circuit includes a fixed-gain amplifier circuit that is coupled to a current path formed by a collector electrode and an emitter electrode of the photo-transistor. A biasing circuit, which is coupled to a base electrode of the photo-transistor, biases the photo-transistor into a saturated state.

Abstract: A system and method for executing sequences of instructions which can be used to access a memory location in a locked fashion. The first instruction specifies an address and sets a lock register which disables interrupts until it is cleared. The second instruction specifies an address and clears the lock register. The second instruction is not executed if the lock register was already cleared and doesn't update memory if the cache line of the first address is no longer valid. If the second address is not cacheable, the instructions are off-loaded to the bus interface and the results of the update are used to update the processor state. The present invention allows locked memory updates and process synchronization without locking of arbitrary duration of the entire shared data structure. The calculation and update of the data structure may continue after a context switch. The present invention is compatible with a wide range of cache-coherence protocols.

Abstract: A system and method for changing an arbitration priority of a bus master are described. A changing system condition can be detected and used to signal the arbiter to change the priority of one or more bus masters. Timers can be provided to delay the request of a changed priority and to return a bus master to its default priority.

Abstract: The present invention, generally speaking, provides an improved base drive arrangement for scan and/or EHT output stages in a television or video display monitor. In accordance with one aspect of the invention, by adding just a few components to an existing main base drive circuit, two power transistors may be driven, e.g. a scan output transistor and an EHT output transistor. The two power transistors are switched at the same time, allowing pulse width modulators of the scan and EHT circuits to operate on a common time base. Switching of two power transistors at the same time would usually require a quite complicated design to offset the different storage times of the two devices, thereby achieving high performance but at a considerable cost premium. The base drive circuit of the invention achieve substantial synchronization of the two transistors at minimal cost.