Abstract: The class AB amplifier is configured to provide low quiescent current while achieving high internal switching rates. The buffer is connected to a large external capacitance which provides external compensation. The amplifier includes an input stage which converts differential voltages to current. An output stage provides an output current and also provides a feedback current into the input stage. A biasing network provides voltage for biasing various nodes within the amplifier. Cross-coupling is provided within the output stage for achieving a low quiescent current. A pair of current limiting circuits, one for p-channel element and another for n-channel elements, is also provided.

Abstract: A method for creating and organizing aliases for flies stored on a computer system in which the stored files are searched according to defined search criteria. For files meeting the search criteria, aliases to the files are created, and the aliases are organized together in a display window for presenting the results of the search to the computer user. The computer continues to perform these searching and organizing functions as the computer is used, so that the information presented is current and up-to-date.

Abstract: A filter capable of having its damping and frequency parameters independently varied. The filter can be represented in either a digital or an analog computation network. The network comprises four multipliers for multiplying by a frequency term twice and a damping factor twice. In addition, the network comprises two unit delay blocks for temporarily storing previous signal input values for zeros or output values for poles. These stored values are used in computing subsequent outputs. The multipliers are configured with adders and subtractors to compute a next output value as a combination of a current input, a weight-2+2df+f.sup.2 -wd.sup.2 f.sup.2 times the most recent saved value and a weight 1-2df+wd.sup.2 f.sup.2 times the previous saved value. Moreover, unity gain at DC can be achieved.

Abstract: A method and apparatus for manipulating inked objects in a computer system includes the steps of displaying a first recognized object on a computer screen and displaying a first ink object on the screen which was previously recognized as the first recognized object. The first ink object is edited to create a second ink object, and the second ink object is recognized as a second recognized object. The first recognized object is then replaced with the second recognized object. The method also preferably includes a step of selecting the first recognized object, and the first ink object is displayed in response to the selection step. A preferred method of selecting the first recognized object is to move a stylus within a predetermined distance or bounding box of the first recognized object.

Abstract: The present invention facilitates the Dynamic Random Access Memory (DRAM) refresh function in a less obtrusive manner than in the prior art. The present invention facilitates the refresh function during idle time when the DRAM is not busy handling read or write transactions. If insufficient idle time exists then the present invention will force a refresh operation thus ensuring that all memory cells are maintained in a properly charged state.

Abstract: From a matrix of elements representing an image, coordinates of each end of lines in a parallel array are generated. The lines in the array join adjacent elements in the same binary state. The coordinates are communicated to a vector graphics device which draws the array of parallel lines to form a graphic representation of the image.

Abstract: A system for bit-masked color signal scaling comprises a processing unit, a display device, and a memory wherein a scaling unit, an image memory, a multiplication image memory, an approximation image memory, an approximation multiplication image memory, and a scaled image memory reside. The scaling unit retrieves a color signal having a red channel signal, a green channel signal, and a blue channel signal from the image memory, and performs either an exact or an approximate bit-masked color signal scaling. A method for exact bit-masked color signal scaling comprises the steps of: generating a staggered masking signal; generating a center masking signal; generating a staggered result signal; generating a center result signal; and adding the staggered result signal and the center result signal to produce a scaled color signal.

Abstract: A digitally signed message, protected with a chain of certificates from the sender's immediate certifier up through an ultimate certifier, is transmitted to a recipient together with the entire certificate chain. The entire certificate chain is stored in a single signer file accessible by the sender. Drag-and-drop gestures of a graphical user interface are used by the sender to sign and certify the message, and an icon is provided on the recipient's display to initiate verification.

Abstract: A system for generating and displaying a contrast false color overlay as a focus assist includes a signal divider, an automatic gain control unit, an adder, a signal reducer and a signal combiner. The signal divider receives a signal representing an image and divides the signal into a red channel signal, a green channel signal and a blue channel signal. The red, green and blue channel signals are input to the signal reducer and respectfully reduced by a percentage value. The reduced Green and Blue channel signals are input to the signal combiner and combined with the output of the adder. A luminance signal is also input or generated from the channel signals and is fed to the automatic gain control unit which produces a contrast signal whose brightness is proportional to the contrast in the image. The contrast signal is input to the adder along with a reduced version of the red channel signal where the two signals are added together, and the output of the adder is provided to the combiner.

Abstract: A telecommunications adapter interfaces computing devices to the analog telephone network, achieving a tightly integrated digital telecommunications link with the analog telephone network. The telecommunications adapter takes advantage of certain host resources including, preferably, the computer's signal processor, the computer's power supply and a computer/peripheral serial interface. System cost for digital communications over the analog network is therefore reduced. Furthermore, the telecommunications adapter is able to accept and deliver a digitized representation of the analog (voice) data stream in real time, supporting both existing and future voice-band communications technologies. Finally, the invention facilitates rapid and inexpensive adaptation to the various international telephone standards. Instead of replacing an entire modem, a relatively inexpensive satellite processor (i.e., the telecom adapter) may be replaced instead.

Abstract: The invention is an instruction for locating the address of a specific character or value within a byte string of variable length. An offset into a portion of the string is specified and the portion of the string is searched for a first occurrence of the specific character beginning at the specified offset. If the specific character is found, then the existence of the specific character is indicated and an address or offset of the specific character is saved or otherwise indicated. If the specific character is not found, then the non-existence of the specific character is indicated and a convenient address or offset for referencing the next character immediately following the portion of the string already examined is saved or otherwise indicated. The specific character can have a length of one or more bytes and can be a pre-defined fixed value or a dynamic arbitrary value. The invention can execute in a time period comparable to performing an arithmetic instruction.

Abstract: Methods and circuitry for arbitrating for control of a serial bus are described. According to one embodiment, one or more nodes of a serial bus are provided with a mechanism for discriminating between data packets and acknowledge packets. If a packet transmitted, repeated, or received by the node is a data packet, the node remains idle for a subaction gap time T.sub.sa to better ensure that the expected acknowledge packet is allowed to successfully propagate throughout the serial bus to the source node. If the packet transmitted by the node is an acknowledge packet, the node is free to begin the arbitration phase of the next subaction if there are no other conditions that prevent further arbitration by that node. To discriminate between data packets and acknowledge packets, a counter is used to determine the length of a transmitted packet, and the length is compared to the expected length of an acknowledge packet.

Abstract: A memory architecture including a memory cache which uses a single level of write buffering in combination with page mode writes to attain zero wait state operation for most memory accesses by a microprocessor. By the use of such a memory architecture, the speed advantages of more expensive buffering schemes, such as FIFO buffering, are obtained using less complex designs. The memory architecture utilizes same page detection logic and latching circuitry and takes advantage of a feature built into industry standard dynamic RAMs, namely page mode writes, to perform writes to memory which allow the processor to be freed before the write is completed for the most frequently occurring type of write operations.

Abstract: A system for shading graphic images for realistic rendering representative of tarnish accumulation has a display device, a central processing unit, an input device, and a memory means. The memory includes image components, shading routines, accessibility routines, display routines, and a texture map. The system modifies each image prior to display to apply shading. The system uses the accessibility routines to produce an accessibility factor for each pixel in the image. The accessibility factor is then used by the display routines to apply the desired shading to each pixel as it is rendered on the display device.

Abstract: An interface device for a point-to-point connected serial bus in which bus clock and bus data transmissions on the bus cease between transmissions of packets of data, includes a low latency resynchronizing circuit and an end of packet detector which is independent of control data within the packet. The resynchronizer is based on an interface which receives bus data and bus clock from a transmission of a packet on the bus. A circular input buffer stores bus data received from the bus in data locations indicated by an input pointer in response to the bus clock. An input pointer generator supplies the input pointers to the input buffer in a circular sequence, beginning in a particular location during a first bus clock in a packet. An output selector supplies bus data from one of the N data locations in the input buffer to the selector output in response to an output pointer and in response to the local clock.

Abstract: A bus circuit for implementing a high speed dominant logic bus for a differential signal. The bus circuit is useful in a communication network having a plurality of multi-port nodes that are coupled by point-to-point links that communicate differential signals. Each port in the node includes a bus driver that receives the differential signal received at the port. The bus driver supplies a differential current signal to a first bus. A terminator circuit is coupled to the first differential bus, to receive the differential current signals supplied from the ports. The terminator circuit, responsive to the differential current signal, outputs a differential voltage signal indicative of either a dominant state or a non-dominant state to a second differential bus, which is coupled to the plurality of ports for transmission.