Abstract: A system for displaying a sequential stream of information on a single display. The system includes a computer for defining an first area on the display and for displaying a first sample of the information within the first area. The first sample represents a first segment of the information. The computer further is for displaying a second sample of the information within the first area of the display. The second sample represents a second segment of the information. The computer is further for displaying a third sample of the information within the first area of the display. The third sample represents a third segment of the information. The first segment includes the second segment and the third segment.
Abstract: A graphical editor user interface that is particularly well suited for use in pointer based computer systems. The graphical editor is arranged to permit the user to easily edit various selected graphic objects. The selected objects are highlighted and preferably editing handles are provided at designated positions relative to the selected portions of the object. Additionally, a bounding box is drawn about the selected portions of the object. In various aspects of the invention, the user is then permitted to edit the object by executing specific actions. The editing actions include resizing, duplicating, distorting and moving either the entire object or only the selected portions. After any of the editing maneuvers is performed, the display is updated to reflect any changes made during the editing step.
Abstract: A system and method for documenting and displaying computer program code comprises a token annotation unit, a comment analyzer, a token parsing library, and a code outline unit. The token parsing library parses a program comprising related program code files into a set of constituent tokens. The token annotation unit selectively associates one or more annotations with tokens in a program by creating a token annotation object. When program code is displayed, the token annotation unit visually identifies each annotated token present according to a display style. The token annotation unit presents annotations corresponding to an annotated token in response to the selection of the annotated token during program code display.
Abstract: A system and method achieve and maintain an accurate white point setting of a CRT display in a computing system. The CRT is initially calibrated by individually driving the individual color cathodes and by measuring tristimulus values and cathode beam current for each of the three primary colors. The tristimulus values are normalized by dividing each value by the beam current producing it, and the normalized values are then stored in a calibration memory contained in the display unit. A table of gamma values representing beam current as a function of video drive voltage is measured and also added to the calibration memory. Calibration of the display is implemented by driving the display controller with a white point value and calculating the cathode beam currents from the stored tristimulus values, required to produce an accurate CRT representation of the signal sent to the display controller.
Abstract: A Text Services Manager (TSM) maintains and uses TSM documents to ensure proper communication between applications and their needed input methods. A TSM document comprises information about the input methods and text services used by a particular instance of an application. One TSM document is preferably associated with each working document represented by an application window. Through use of the TSM document, the TSM provides for multiple instances of a particular input method, and the automatic synchronization of the input method to the active window. The preferred embodiment of the present invention comprises novel methods that provide this functionality including: methods for opening or closing a TSM aware application, methods for creating and disposing of TSM documents, and methods for activating and deactivating a TSM document.
Type:
Grant
Filed:
February 19, 1993
Date of Patent:
April 23, 1996
Assignee:
Apple Computer, Inc.
Inventors:
Kenny S. C. Tung, John Harvey, Yasuo Kida, Christopher S. Derossi, Keisuke Hara, Nobuhiro Miyatake
Abstract: A polycyclic timing system and an apparatus for pipelined computer operation comprises a master state machine and a slave state machine. The master state machine produces a plurality of control signals in response to a clock signal. The master state machine comprises an oscillator, a plurality of data storage elements, and a next state feedback network. The oscillator is used to produce a clock signal that triggers the storage elements. The next state feedback network determines the control signals to output based on the current output data storage elements using logic in the next state feedback network. The slave state machine receives the control signals and uses them to produce several asynchronous pulse streams. The slave state machine preferably comprises a plurality of pulse forming state machines and a plurality of pulse transmission amplifiers.
Abstract: A dynamic, multi-speed bus architecture comprising a plurality of variable speed, fixed size links for coupling a plurality of devices together in an arbitrary network arrangement in which each device coupled to the bus comprises a novel communications node having a scalable interface for enabling the local hosts of the devices to communicate via the multi-speed bus. The interface provided within each node comprises a first module and a second module interconnected via a fixed speed, variable size bus. The first module is coupled to the local host of a device via a fixed speed, fixed size bus for converting a first data packet received from the local host into a second data packet of an appropriate form for transmission on the fixed speed, variable size bus disposed between the two modules. The second module receives the second data packet and converts it into a third data packet of an appropriate form for transmission onto the variable speed, fixed size link coupling the device to the multi-speed bus.
Abstract: A system for processing and recording digitized component television signals onto analog video tape includes a digital color transformation matrix for generating a digital luminance signal, a first digital chrominance signal, and a second digital chrominance signal. The signals are then sample rate reduced, interleaved, and stored in a storage subsystem, which may include a disk array. The storage subsystem allows a constant rate, uninterrupted data stream to be produced. To record the signals onto video tape, the signal data is read from the storage subsystem and separated. A series of digital signal processing elements, coupled to the digital luminance signal (read from the storage subsystem), are used to generate a digital filtered and frequency modulated luminance signal.
Type:
Grant
Filed:
April 1, 1994
Date of Patent:
April 16, 1996
Assignee:
Apple Computer, Inc.
Inventors:
David K. Stevenson, Henry N. Kannapell, Lawrence F. Heyl
Abstract: A method is described for optimizing printing a first print dot, a second print dot, a third print dot, and a fourth print dot adjacent to each other on a sheet of paper. The method first determines whether the first, second, third, and fourth print dots to be printed are in black color. If any one of the first, second, third, and fourth print dots is in the black color, then the respective one of first, second, third, and fourth print dots needs to be double printed with the black color. If the first and second print dots are in the black color and the third and fourth print dots are color print dots, then the first and second print dots are printed with the black color and the third color print dot is printed during a first print pass by the printer.
Type:
Grant
Filed:
June 30, 1993
Date of Patent:
April 9, 1996
Assignee:
Apple Computer, Inc.
Inventors:
Stuart L. Claassen, Joseph Ku, Anitta L. Bliss
Abstract: Circuitry is described for providing a telephone line interface circuit of a MODEM for a computer with an AC impedance and DC voltage/current characteristics required by a given type telephone network such that the telephone line interface circuit can be matchingly connected with the given type telephone network. The given type telephone network provides an identification code representative of the required AC impedance and DC voltage/current characteristics. The circuitry comprises a plurality of impedance components that, when connected to the telephone line interface circuit, determine the AC impedance and DC voltage/current characteristics of the telephone line interface circuit. A plurality of terminals are coupled to receive a plurality of control signals associated with the identification code.
Type:
Grant
Filed:
August 25, 1994
Date of Patent:
April 9, 1996
Assignee:
Apple Computer, Inc.
Inventors:
Robert Cox, Eric Gradeler, Barry Hochfield, Philippe Le Bars, Rodger J. Mohme, Steven J. Young
Abstract: The present invention reduces the overhead commonly associated with computer queues by not requiring direct addressing of each location in the queue and by not requiring specialized underflow logic. Furthermore, reads and writes to the computer queue of the present invention can be asynchronous. Lastly, the computer queue of the present invention requires less circuitry and is thus physically smaller, requires less power to operate and can operate more quickly than can queues of the prior art.
Abstract: A unitary heat sink including a planar contact portion for contacting the top of an IC. The heat sink is constructed from a material having a thermal conductivity of at least 150 watts per meter Degree Kelvin (W/m.degree.K.) but preferably is constructed from aluminum having a conductivity of 221 (W/m.degree.K.). A number of leg portions extend from the contact portion such that each leg portion has a distal end. The leg portions, being made of the same material as the contact portion, are configured to have a sufficient resiliency such that deformations of the leg portions provide a spring force in the range of 5 to 16 lbs against the top of the IC. A method for dissipating heat from an integrated circuit includes the steps of forming a unitary heat sink from a heat sink material, where the heat sink includes a contact portion and a number of integral, spring leg portions.
Abstract: The present invention is directed to a system for routing data between rings. A routing symbol is provided, and as it crosses a bridge, the local target address of the bridge is dropped, and the local source address of the bridge node (in the far side ring) is added to the routing symbol. Fields are shifted in the routing symbol so that the value that was in a hop field becomes the local target address in the new ring. Because the routing symbol that arrives at the ultimate target has been transformed into a source node list, the return path is available to the target.
Abstract: The class AB amplifier is configured to provide low quiescent current while achieving high internal switching rates. The buffer is connected to a large external capacitance which provides external compensation. The amplifier includes an input stage which converts differential voltages to current. An output stage provides an output current and also provides a feedback current into the input stage. A biasing network provides voltage for biasing various nodes within the amplifier. Cross-coupling is provided within the output stage for achieving a low quiescent current. A pair of current limiting circuits, one for p-channel element and another for n-channel elements, is also provided.
Abstract: A method for creating and organizing aliases for flies stored on a computer system in which the stored files are searched according to defined search criteria. For files meeting the search criteria, aliases to the files are created, and the aliases are organized together in a display window for presenting the results of the search to the computer user. The computer continues to perform these searching and organizing functions as the computer is used, so that the information presented is current and up-to-date.
Abstract: A filter capable of having its damping and frequency parameters independently varied. The filter can be represented in either a digital or an analog computation network. The network comprises four multipliers for multiplying by a frequency term twice and a damping factor twice. In addition, the network comprises two unit delay blocks for temporarily storing previous signal input values for zeros or output values for poles. These stored values are used in computing subsequent outputs. The multipliers are configured with adders and subtractors to compute a next output value as a combination of a current input, a weight-2+2df+f.sup.2 -wd.sup.2 f.sup.2 times the most recent saved value and a weight 1-2df+wd.sup.2 f.sup.2 times the previous saved value. Moreover, unity gain at DC can be achieved.