Patents Assigned to Applied Digital Access, Inc.
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Patent number: 7100092Abstract: A protocol analysis access system (“PAAS”) and a restricted access method for remotely monitoring and testing embedded channels in a signal communicated over a telecommunications network. The PAAS system is capable of accessing a signal from a network circuit through digital cross-connect systems (“DCSs”) or through direct connections. In case of restricted network access, the PAAS performs non-intrusive monitor-only function on the signal without interfering with or interrupting the data flow over the network circuit. In addition, the PAAS system is capable of performing non-intrusive conformance testing on a signal using a protocol analyzer. In case of non-restricted network access, the PAAS system allows full performance testing on a signal. The PAAS system functions are executed by an external command source from a remote network maintenance center via remote control links. The monitor-only and test results are reported back to the remote network maintenance center for further analysis.Type: GrantFiled: February 7, 2003Date of Patent: August 29, 2006Assignee: Applied Digital Access, Inc.Inventors: Lorin Allred, Derek J. Nelson, Mark Milliman
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Patent number: 7072305Abstract: A method and system for testing at least one link in a communications network. The system includes first and second analyzer units that are configured to test an existing link in the network. Alternatively, the first and second analyzer units may be configured to establish and test a link between them. A computer remotely controls the first and second analyzer units to perform testing of various communication parameters, such as packet loss and latency. Each analyzer unit may be configured to collect data over a predetermined duration to establish a network baseline of operation, which may be used to detect future network malfunctions. The computer estimates the deviation of communication parameters from the network baseline.Type: GrantFiled: October 29, 1999Date of Patent: July 4, 2006Assignee: Applied Digital Access, Inc.Inventor: J. Michael Gregson
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Patent number: 6819655Abstract: A method and system for analyzing a public switched communications network from a remote place via the public Internet. The system comprises an access device which collects data from one or more links in a public switched communications network. The system further includes a server computer which receives the collected data from the access device via a dedicated network or the Internet. The server computer executes one or more applications to perform protocol analysis based on the received data. A client computer executing a Web browser may be used to communicate with the server computer via the Internet and access the outcome of the protocol analysis.Type: GrantFiled: November 9, 1998Date of Patent: November 16, 2004Assignee: Applied Digital Access, Inc.Inventor: J. Michael Gregson
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Patent number: 6519723Abstract: A protocol analysis access system (“PAAS”) and a restricted access method for remotely monitoring and testing embedded channels in a signal communicated over a telecommunications network. The PAAS system is capable of accessing a signal from a network circuit through digital cross-connect systems (“DCSs”) or through direct connections. In case of restricted network access, the PAAS performs non-intrusive monitor-only function on the signal without interfering with or interrupting the data flow over the network circuit. In addition, the PAAS system is capable of performing non-intrusive conformance testing on a signal using a protocol analyzer. In case of non-restricted network access, the PAAS system allows full performance testing on a signal. The PAAS system functions are executed by an external command source from a remote network maintenance center via remote control links.Type: GrantFiled: September 27, 1996Date of Patent: February 11, 2003Assignee: Applied Digital Access, Inc.Inventors: Lorin D. Allred, Derek J. Nelson, Mark Milliman
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Patent number: 6421323Abstract: A method and apparatus for automated sectionalization of a DS1/DS3 data path based upon information received at a single location along the path. A test and monitor device is located at a point of demarcation between an LEC and an IEC. A Remote Module is located at a point of demarcation between the LEC and CPE. The test and monitor device is fully ANSI compatible. The information that is received is processed in a three step process in order to generate a “Sectionalizer Report”. In preparing the Sectionalizer Report, the information output from a filter is used to determine where particular Events originated.Type: GrantFiled: September 12, 1996Date of Patent: July 16, 2002Assignee: Applied Digital Access, Inc.Inventors: Derek J. Nelson, Paul R. Hartmann, Edward S. Tyburski
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Patent number: 6091712Abstract: A method and apparatus for storing and communicating information regarding the condition of signals which pass through the network interface between customer premises equipment and a local exchange carrier in a telecommunications system. Information stored at the network interface can be sent as a message which is encoded within the payload, within the frame bits, or within the data link. The information that is stored at the network interface is sectionalized to reduce the amount of information that need be sent and to reduce the processing required by the receiving device.Type: GrantFiled: December 24, 1996Date of Patent: July 18, 2000Assignee: Applied Digital Access, Inc.Inventors: Kevin T. Pope, Maynard A. Wright, Daniel A. Strich, Paul R. Hartmann, Edward T. Ellebracht, Douglas B. Ramsayer
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Patent number: 5956324Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.Type: GrantFiled: October 30, 1997Date of Patent: September 21, 1999Assignee: Applied Digital Access, Inc.Inventors: Thomas L. Engdahl, Paul R. Hartmann, Kevin Pope, Kevin Cadieux
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Patent number: 5790531Abstract: A method and apparatus for automated sectionalization of a DS1/DS3 data path based upon information received at a single location along the path. A test and monitor device is located at a point of demarcation between an LEC and an IEC. A Remote Module is located at a point of demarcation between the LEC and CPE. The test and monitor device is fully ANSI compatible. The information that is received is processed in a three step process in order to generate a "Sectionalizer Report". In preparing the Sectionalizer Report, the information output from a filter is used to determine where particular Events originated. A Remote Alarm Indication-Customer Installation signal is generated to enhance the ability to sectionalize the data path.Type: GrantFiled: September 30, 1996Date of Patent: August 4, 1998Assignee: Applied Digital Access, Inc.Inventors: Edward T. Ellebracht, Paul R. Hartmann, Ramone A. Hecker, Kevin T. Pope, Maynard A. Wright
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Patent number: 5774456Abstract: A method and apparatus for automated sectionalization of a DS1/DS3 data path based upon information received at a single location along the path. A test and monitor device is located at a point of demarcation between an LEC and an IEC. A Remote Module is located at a point of demarcation between the LEC and CPE. The test and monitor device is fully ANSI compatible. The information that is received is processed in a three step process in order to generate a "Sectionalizer Report". In preparing the Sectionalizer Report, the information output from a filter is used to determine where particular Events originated. Supplimental Performance Report Messages are generated to enhance the ability to sectionalize the data path.Type: GrantFiled: September 30, 1996Date of Patent: June 30, 1998Assignee: Applied Digital Access, Inc.Inventors: Edward T. Ellebracht, Paul R. Hartmann, Ramone A. Hecker, Kevin T. Pope, Maynard A. Wright
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Patent number: 5757776Abstract: A method and apparatus for automated sectionalization of a DS1/DS3 data path based upon information received at a single location along the path. A test and monitor device is located at a point of demarcation between an LEC and an IEC. A Remote Module is located at a point of demarcation between the LEC and CPE. The test and monitor device is fully ANSI compatible. The information that is received is processed in a three step process in order to generate a "Sectionalizer Report". In preparing the Sectionalizer Report, the information output from a filter is used to determine where particular Events originated. An Alarm Indication Signal-Customer Installation signal is generated to enhance the ability to sectionalize the data path.Type: GrantFiled: September 30, 1996Date of Patent: May 26, 1998Assignee: Applied Digital Access, Inc.Inventors: Edward T. Ellebracht, Paul R. Hartmann, Ramone A. Hecker, Kevin T. Pope, Maynard A. Wright
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Patent number: 5623480Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and substrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.Type: GrantFiled: May 26, 1995Date of Patent: April 22, 1997Assignee: Applied Digital Access, Inc.Inventors: Paul R. Hartmann, Thomas L. Engdahl, Kevin Cadieux, Kevin Pope
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Patent number: 5621720Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. A second embodiment of the invention partitions the system into a base subsystem, a communications link and a remote subsystem, collectively referred to as a distributed architecture system. The distributed architecture system provides all of the performance monitoring and testing capabilities of the existing access system. The distributed architecture system provides a mechanism to transport a plurality of asynchronous and rate independent signals across the link to permit remote testing of digital and voice DS0 frequency circuits. In the preferred embodiment, the link that connects the base to the remote system is a standard DS1 channel.Type: GrantFiled: February 14, 1996Date of Patent: April 15, 1997Assignee: Applied Digital Access, Inc.Inventors: Jeffery S. Bronte, Mark J. Lever, Kevin T. Pope, Paul R. Hartmann
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Patent number: 5581228Abstract: A DS3 level access, monitor and test system including a digital comparator for a telephone network. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.Type: GrantFiled: May 26, 1995Date of Patent: December 3, 1996Assignee: Applied Digital Access, Inc.Inventors: Kevin Cadieux, Paul R. Hartmann, Kevin Pope
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Patent number: 5557616Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.Type: GrantFiled: May 26, 1995Date of Patent: September 17, 1996Assignee: Applied Digital Access, Inc.Inventors: Kevin Cadieux, Paul R. Hartmann
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Patent number: 5553056Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. A second embodiment of the invention partitions the system into a base subsystem, a communications link and a remote subsystem, collectively referred to as a distributed architecture system. The distributed architecture system provides all of the performance monitoring and testing capabilities of the existing access system. The distributed architecture system provides a mechanism to transport a plurality of asynchronous and rate independent signals across the link to permit remote testing of digital and voice DS0 frequency circuits. In the preferred embodiment, the link that connects the base to the remote system is a standard DS1 channel.Type: GrantFiled: October 24, 1994Date of Patent: September 3, 1996Assignee: Applied Digital Access, Inc.Inventors: Jeffery S. Bronte, Mark J. Lever, Kevin T. Pope, Paul R. Hartmann
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Patent number: 5500853Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization, and also provides alarm correlation and hierarchical event filtering.Type: GrantFiled: November 23, 1993Date of Patent: March 19, 1996Assignee: Applied Digital Access, Inc.Inventors: Thomas L. Engdahl, Edward Tyburski, Paul R. Hartmann
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Patent number: 5495470Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization, and also provides alarm correlation and hierarchical event filtering.Type: GrantFiled: November 23, 1993Date of Patent: February 27, 1996Assignee: Applied Digital Access, Inc.Inventors: Edward Tyburski, Paul R. Hartmann