Patents Assigned to Applied Intellectual Properties Co., Ltd.
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Patent number: 7741697Abstract: The present invention discloses a semiconductor device, the device comprising a semiconductor layer on a substrate. A gate oxide and a gate electrode are formed on the semiconductor substrate. A gate conductive layer is formed on the gate electrode. A first doped region is formed in the semiconductor layer. A dielectric spacer is optionally formed onto the sidewall of the gate electrode and part of the semiconductor layer. A second doped region is formed from a predetermined distance to the gate electrode, wherein the predetermined distance is no less than the distance between the first doped region and the gate electrode. A third doped region is formed adjacent to the first doped region in the semiconductor layer and between the first doped region and the second doped region.Type: GrantFiled: April 17, 2007Date of Patent: June 22, 2010Assignee: Applied Intellectual Properties Co., Ltd.Inventor: Yuan-Feng Chen
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Patent number: 7457154Abstract: A memory system comprising a memory array having a plurality of memory units, a column decoder, a row decoder, a selecting/driving circuit and a sensing circuit is disclosed. Each memory unit comprises a gate electrode coupled to a word lines, a source region coupled to a source line or a first bit line, a drain region coupled to a drain line or a second bit line, a first spacer between the source region and the gate electrode and a second spacer between the drain region and the gate electrode. When a first-bit program operation is performed on the memory unit, a switch-on signal is applied to the gate, a programming signal is applied to the source region and the drain region is switched to ground. As the memory unit is activated, the carriers are injected and stored in a first spacer, thus represents a first bit in the memory unit.Type: GrantFiled: June 2, 2006Date of Patent: November 25, 2008Assignee: Applied Intellectual Properties Co., Ltd.Inventors: Tzu-shih Yen, Erik S. Jeng
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Patent number: 7375394Abstract: The present invention includes a semiconductor layer formed over an insulation layer and a substrate. Doped regions are formed in a portion of the semiconductor layer. A gate dielectric and a gate are respectively formed over the semiconductor layer. The arrangement of the gate sidewall and semiconductor layer surface is substantially orthogonal, multi-portion dielectric layer is formed on the gate and a portion of the silicon layer. Charge trapping dielectrics are attached on the multi-portion dielectric layer acting as carrier trapping structure. The gate-to-source/drain non-overlapped implantation is capable of storing multi-bits per transistor.Type: GrantFiled: July 6, 2005Date of Patent: May 20, 2008Assignee: Applied Intellectual Properties Co., Ltd.Inventor: Erik S. Jeng
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Patent number: 7235848Abstract: The present invention discloses a nonvolatile memory with spacer trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide. An isolation layer is formed over the sidewall of the gate structure. First spacers are formed on the sidewall of the isolation layer and becoming the spacer trapping structure for storing carrier. And the p-n junctions of source and drain regions are formed adjacent to the gate structure. Silicide is formed on the gate structure and the source and drain regions.Type: GrantFiled: December 9, 2003Date of Patent: June 26, 2007Assignee: Applied Intellectual Properties Co., Ltd.Inventor: Erik S. Jeng
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Patent number: 7072210Abstract: A memory array including a plurality of word lines, a plurality of first source/drain lines, a plurality of second source/drain lines, and a plurality of memory units. Each memory unit includes a gate electrode coupled to one of the word lines, a first source/drain region coupled to one of the first source/drain lines or first bit lines, a second source/drain region coupled to one of the second source/drain lines or second bit lines, a first spacer between the first source/drain region and the gate electrode to store electrons or electric charges, and a second spacer between the second source/drain region and the gate electrode to store electrons or electric charges.Type: GrantFiled: April 26, 2004Date of Patent: July 4, 2006Assignee: Applied Intellectual Properties Co., Ltd.Inventor: Erik S. Jeng
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Patent number: 7030448Abstract: The structure of the nonvolatile memory includes a substrate having source/drain formed at unselected sides and source/drain with extension source/drain formed at other selected sides. A gate dielectric layer is formed on the substrate and a gate is formed on the gate dielectric layer. An isolation layer is formed along the surface of the gate. Spacers are formed attached on the sidewalls of the gate.Type: GrantFiled: January 12, 2004Date of Patent: April 18, 2006Assignee: Applied Intellectual Properties Co., Ltd.Inventor: Erik S. Jeng
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Publication number: 20050227420Abstract: The structure of the nonvolatile memory comprises a substrate having source/drain formed at unselected sides and source/drain with extension source/drain formed at other selected sides. A gate dielectric layer is formed on the substrate and a gate is formed on the gate dielectric layer. An isolation layer is formed along the surface of the gate. Spacers are formed attached on the sidewalls of the gate.Type: ApplicationFiled: May 23, 2005Publication date: October 13, 2005Applicant: Applied Intellectual Properties Co., Ltd.Inventor: Erik Jeng
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Patent number: 6903968Abstract: A nonvolatile memory capable of storing multi-bits binary information is provided. The memory includes an oxide formed on a substrate. A control gate is formed on the oxide. An L-shape structure is attached on sidewall of the control gate. Spacers are formed on the L-shape structure to act as a floating gate. A first doped region and a second doped region is formed in the substrate adjacent to the spacers with a channel between the two doped regions. Wherein the spacer represent a first binary status by injecting and storing electrical charges in the spacers. Or to represent a second binary status by not injecting electrical charges into the spacer.Type: GrantFiled: January 22, 2004Date of Patent: June 7, 2005Assignee: Applied Intellectual Properties Co., Ltd.Inventor: Erik S. Jeng
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Patent number: 6885072Abstract: The present invention discloses a nonvolatile memory with undercut trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide, wherein the gate structure including a undercut structure formed at lower portion of the gate structure and inwardly into the gate structure. An isolation layer is formed over the sidewall of the gate structure. First spacers are formed on the sidewall of the isolation layer and filled into the undercut structure for storing carrier and source and drain regions formed adjacent to the gate structure and under the undercut structure. Salicide is formed on the gate structure and the source and drain regions.Type: GrantFiled: November 18, 2003Date of Patent: April 26, 2005Assignee: Applied Intellectual Properties Co., Ltd.Inventor: Erik S. Jeng
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Patent number: 6740927Abstract: A nonvolatile memory capable of storing multi-bits binary information is provide. The memory includes an oxide formed on a substrate. A control gate is formed on the oxide. An L-shape structure is attached on sidewall of the control gate. Spacers are formed on the L-shape structure to act as a floating gate. A first doped region and a second doped region is formed in the substrate adjacent to the spacers with a channel between the two doped regions. Wherein the spacers represent a first binary status by injecting and storing electrical charges in the spacers. Or to represent a second binary status by not injecting electrical charges into the spacer.Type: GrantFiled: January 6, 2003Date of Patent: May 25, 2004Assignee: Applied Intellectual Properties Co., Ltd.Inventor: Erik S. Jeng