Abstract: The present invention relates to a combined approach of image and template correlation, and vector correlation wherein edge detection and pattern searching are joined in a single operation to provide great flexibility without requiring extensive computational facilities. A template is devised from a sparse set of coordinate points that model only the important edges of an object to be located within an image. Different templates are dynamically reconstructed as an estimation of the object location within the image becomes more precise.

Abstract: A method and apparatus is disclosed for converting an interlaced television display to a progressive, scan, or non-interlaced display where artifacts are removed if the source of the signal is from a movie film to television converter, a video recording of a movie, a live camera, or a camera output captured on a video recording system, or any sequence of the above, by utilizing three motion detection stages.

Abstract: The present invention relates to a combined approach of image and template correlation, and vector correlation wherein edge detection and pattern searching are joined in a single operation to provide great flexibility without requiring extensive computational facilities. A template is devised from a sparse set of coordinate points that model only the important edges of an object to be located within an image. Different templates are dynamically reconstructed as an estimation of the object location within the image becomes more precise.

Abstract: A parallel processing system for processing data matrices, such as images, is disclosed. The system includes a plurality of processing units, organized in four blocks of eight processing units per processing chip, and external cache burst memory, wherein each processing unit is associated with at least one column of the external memory. A barrel shifter connected between the memory and the processing units allows data to be shifted to adjacent processing chips, thus providing the means for connecting several of the chips into a ring structure. Further, digital delay lines are connected between the barrel shifter and the processing units, thus providing the capability of delaying, via a predetermined number of clock cycles, incoming column data. Each processing unit is provided with a nine bit cache memory.

Abstract: An illumination system having a lighting dome, a vertical light source, an image acquisition means, and a light controlling means, a system controller and a three-axis servo system wherein the dome is of unitary printed circuit board construction populated with a plurality of surface mounted light emitting diodes is disclosed. The dome has a first longitudinal axis and is bendable along hinges formed through the circuit board to define a partially enclosed dome having eight octants or sections, each section having an upper and lower tier portion defining a plurality of planar illumination banks, which illuminate an object from 360.degree. around the object and from predetermined angles relative to the first longitudinal axis. The vertical light source, which is a planar printed circuit board populated with surface mounted LEDs, and the beam splitter are provided for illumination of the object with light parallel to the first longitudinal axis.

Abstract: A system and method for floating point computations involving matrices or vectors includes a plurality of identical processing units connected to a linear chain with direct data communication links between adjacent processing units. Each such processor is also connected to its own private memory. A sequence of instructions is sent by a controller to all floating point processing units and their associated memories whereby all processing units in the chain receive the same instruction and all memories receive the same address at any given cycle in the instruction sequence. Each processing unit internally handles floating point operations such as normalization, sign changes, and multiplication in a bit serial manner.

Abstract: A system for processing data matrices such as images and spatially related data includes a plurality of neighborhood processing units connected in a linear chain with direct data communication links between adjacent processing units. A sequence of instructions are sent to the processing units by a single controller, where all neighborhood processing units in the system receive the same instruction at any given cycle in the instruction sequence. The width of the data matrix array is the same as a number of processors, so that there is one processor per column in the data matrix. The memory associated with each processor is external and large enough to hold the entire image or data matrix. The processors are able to operate arithmetically in a serial or parallel mode, where an efficient means is provided to transpose 8.times.8 bit submatrices between the two modes. An indirect addressing means is provided which operates on byte-wide memories external to the processing unit.

Abstract: A device useful for illuminating parts to be inspected includes an illumination device employing a plurality of bundles of optical fibers coupled with a light source. The device includes a housing having an optical lens in one end which has an outer surface that is convex about a single axis. A clamp assembly mounts the bundles on the opposite end of the housing, with the ends of the bundles extending through a rectangular opening in an end wall of the housing. An aperture plate between the lens and the ends of the bundles masks light from the bundles so that all of the light passing through the aperture plate falls on the lens, thereby partially collimating the light impinging on the inner face of the lens.