Abstract: A method of depositing a silicon oxide layer over a substrate includes providing a substrate to a deposition chamber. A first silicon-containing precursor, a second silicon-containing precursor and a NH3 plasma are reacted to form a silicon oxide layer. The first silicon-containing precursor includes at least one of Si—H bond and Si—Si bond. The second silicon-containing precursor includes at least one Si—N bond. The deposited silicon oxide layer is annealed.

Abstract: A substrate is disposed within a processing chamber. A nitrogen precursor and a group-III precursor are flowed into the processing chamber. A layer is deposited over the substrate with a thermal chemical-vapor-deposition process at an elevated temperature within the processing chamber using the nitrogen precursor and the group-III precursor. Light beams are directed to a surface of the layer and light spots corresponding to reflections of the light beams are received from the surface at a position-sensitive detector. Positions of the light spots on the position-sensitive detector are determined from photocurrent induced in a photodiode in the position-sensitive detector. A curvature of the layer is determined from the positions of the light spots.

Abstract: Embodiments in accordance with the present invention relate to multi-stage curing processes for chemical vapor deposited low K materials. In certain embodiments, a combination of electron beam irradiation and thermal exposure steps may be employed to control selective outgassing of porogens incorporated into the film, resulting in the formation of nanopores. In accordance with one specific embodiment, a low K layer resulting from reaction between a silicon-containing component and a non-silicon containing component featuring labile groups, may be cured by the initial application of thermal energy, followed by the application of radiation in the form of an electron beam.

Abstract: A method for fabricating a semiconductor device with adjacent PMOS and NMOS devices on a substrate includes forming a PMOS gate electrode with a PMOS hardmask on a semiconductor substrate with a PMOS gate dielectric layer in between, forming an NMOS gate electrode with an NMOS hardmask on a semiconductor substrate with an NMOS gate dielectric layer in between, forming an oxide liner over a portion of the PMOS gate electrode and over a portion of the NMOS gate electrode, forming a lightly doped N-Halo implant, depositing a nitride layer over the oxide liner, depositing photoresist on the semiconductor substrate in a pattern that covers the NMOS device, etching the nitride layer from the PMOS device, wherein the etching nitride layer leaves a portion of the nitride layer on the oxide liner, etching semiconductor substrate to form a Si recess, and depositing SiGe into the Si recesses, wherein the SiGe and the nitride layer enclose the oxide liner.

Abstract: A semiconductor device includes a substrate having regions filled with an additive that forms a source/drain for a MOS device, a gate dielectric layer deposited over the substrate, the gate dielectric layer electrically isolates the substrate from subsequently deposited layers, a gate electrode deposited over the gate dielectric layer, an oxide liner formed along laterally opposite sidewalls of the gate electrode, a nitride layer formed along the oxide liner extending above the gate electrode, and wherein the additive and the nitride layer enclose the gate electrode.

Abstract: Systems are disclosed for fabricating compound nitride semiconductor structures. The systems include a housing defining a processing chamber, a substrate holder disposed within the processing chamber, an NH3 source, a group-III precursor source, an ultraviolet source, and a CVD showerhead disposed over the substrate holder. The showerhead has a first plenum fluidicly coupled with the NH3 source, with the first plenum having channels fluidicly coupled with an interior of the processing chamber. The first plenum is optically coupled with the ultraviolet light source at an ultraviolet wavelength to receive light transmitted by the ultraviolet light source within the first plenum. The CVD showerhead also has a second plenum fluidicly coupled with the group-III precursor source, with the second plenum having channels fluidicly coupled with the interior of the processing chamber.

Abstract: An integrated system for baking and chilling wafers includes a heater for heating a wafer to an elevated temperature, a chiller for cooling the wafer, and a shuttle operatively connected to the heater and the chiller for transferring the wafer between the heater and the chiller. The chiller further includes a low thermal mass wafer support for providing support to a bottom surface of a wafer and a chill plate coupled to the low thermal mass wafer support for cooling the wafer. The low thermal mass wafer support has a higher thermal conductivity in the plane parallel to the bottom surface of the wafer than in the direction perpendicular to the bottom surface of the wafer. The low thermal mass wafer support can further include a plurality of proximity pins for supporting the wafer.

Abstract: Embodiments in accordance with the present invention relate to techniques for enhancing uniformity of plasma-based semiconductor processing. In one technique, the exterior of a plasma-based processing chamber features a series of substantially continuous plates composed of a material exhibiting a low permeability to magnetic fields. This high-? shielding material is utilized to block exposure of a plasma within the chamber to the effects of external magnetic fields. Embodiments in accordance with the present invention are effective to shield plasma-based processing chambers from external magnetic fields originating from adjacent clustered chambers, and/or from the earth's geomagnetic field.

Abstract: Methods and systems of diagnosing an arcing problem in a semiconductor wafer processing chamber are described. The methods may include coupling a voltage probe to a process-gas distribution faceplate in the processing chamber, and activating an RF power source to generate a plasma between the faceplate and a substrate wafer. The methods may also include measuring the DC bias voltage of the faceplate as a function of time during the activation of the RF power source, where a spike in the measured voltage at the faceplate indicates an arcing event has occurred in the processing chamber. Methods and systems to reduce arcing in a semiconductor wafer processing chamber are also described.

Abstract: Critical Dimension (CD) of features on a semiconductor substrate may be indicated utilizing the site-specific binding properties of organic or biological molecules. In accordance with one embodiment of the present invention, a fluorescent tagged organic molecule is fabricated having a length corresponding to the desired CD. The semiconductor substrate is exposed to a solution containing the organic molecule. The solution is then removed and the structure analyzed for the presence of the fluorescent tag, indicating a feature having the desired CD. Fluorescent tagged biological molecules of known size such as peptides or proteins, or nucleic acids such as DNA or RNA, may also be employed for CD measurement. Alternatively, a CD marker molecule may be designed to exhibit preferential binding, such that it fails to bind to the substrate in instances of incomplete resist development or etching.

Abstract: A method of calculating a process parameter for a deposition of an epitaxial layer on a substrate. The method includes the steps of measuring an effect of the process parameter on a thickness of the epitaxial layer to determine a gain curve for the process parameter, and calculating, using the gain curve, a value for the process parameter to achieve a target thickness of the epitaxial layer. The value is calculated to minimize deviations from the target thickness in the layer. Also, a substrate processing system comprising that includes a processor to calculate a value for the process parameter to achieve a substantially uniform epitaxial layer of a target thickness on the substrate, where the value is calculated using a gain curve derived from measurements of layer uniformity as a function of the value of the process parameter.

Abstract: Compressive stress in a film of a semiconductor device may be controlled utilizing one or more techniques, employed alone or in combination. A first set of embodiments increase silicon nitride compressive stress by adding hydrogen to the deposition chemistry, and reduce defects in a device fabricated with a high compressive stress silicon nitride film formed in the presence of hydrogen gas. A silicon nitride film may comprise an initiation layer formed in the absence of a hydrogen gas flow, underlying a high stress nitride layer formed in the presence of a hydrogen gas flow. A silicon nitride film formed in accordance with an embodiment of the present invention may exhibit a compressive stress of 2.8 GPa or higher.

Abstract: A chuck for a semiconductor workpiece features integrated resistive heating and electrostatic bipolar chucking elements on a thermal pedestal. These integrated heating and chucking elements maintain wafer flatness, as well as uniformity of an underlying gap accommodating a thermal gas between the workpiece and the chuck. In accordance with one embodiment of the present invention, a laminated Kapton wafer heater is attached to the top of the thermal surface, under the wafer: At least two electrical voltage zones are isolated within the heater, in order to create a chucking force between the chuck and the wafer without having to contact the wafer with an electrical conductor. These voltage zones can be created by using separate conducting elements as well as by imposing a DC bias on zones including the resistive heating elements.

Abstract: Methods are provided of depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A silicon-containing gas, an oxygen-containing gas, and a fluent gas are flowed into the substrate processing chamber. The fluent gas has an average molecular weight less than 5 amu. A first high-density plasma is formed from the silicon-containing gas, the oxygen-containing gas, and the fluent gas to deposit a first portion of the silicon oxide film over the substrate and within the gap with a first deposition process that has simultaneous deposition and sputtering components having relative contributions defined by a first deposition/sputter ratio.

Abstract: An apparatus for dispensing fluid during semiconductor substrate processing operations. The apparatus includes a first processing chamber, a second processing chamber, and a dispense arm assembly. The apparatus further includes a dispense arm access shutter positioned between the first and second processing chambers and moveable between an open and a closed position. The dispense arm assembly can travel from the first processing chamber to the second processing chamber when the dispense arm assembly is in the open position.

Abstract: A gas distributor for use in a semiconductor processing chamber is provided. The gas distributor comprises a gas inlet, a gas outlet, and a stem section having a spiral thread. The gas distributor further comprises a body having a gas deflecting surface that extends radially outward away from the stem section and a lower face disposed on the opposite side of the body from the gas deflecting surface, a lateral seat disposed between the spiral thread and the gas deflecting surface, and a gas passageway that extends from the gas inlet through the stem section and body to the gas outlet. In a specific embodiment, the lateral seat is adapted to hold a sealing member.

Abstract: A silicon oxide film is deposited on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A liquid Si—C—O—H precursor is vaporized. A flow of the vaporized liquid Si—C—O—H precursor is provided to the substrate processing chamber. A gaseous oxidizer is also flowed to the substrate processing chamber. A deposition plasma is generated inductively from the precursor and the oxidizer in the substrate processing chamber, and the silicon oxide film is deposited over the substrate and within the gap with the deposition plasma.

Abstract: A chemical vapor deposition method for forming a dielectric material in a trench formed on a substrate. The method includes flowing a silicon-containing precursor into a process chamber housing the substrate, flowing an oxidizing gas into the chamber, and providing a hydroxyl-containing precursor in the process chamber. The method also includes reacting the silicon-containing precursor, oxidizing gas and hydroxyl-containing precursor to form the dielectric material in the trench. The ratio of the silicon-containing precursor to the oxidizing gas flowed into the chamber is increased over time to alter a rate of deposition of the dielectric material.

Abstract: A method of annealing a substrate comprising a trench containing a dielectric material, the method including annealing the substrate at a first temperature of about 200° C. to about 800° C. in a first atmosphere comprising an oxygen containing gas, and annealing the substrate at a second temperature of about 800° C. to about 1400° C. in a second atmosphere lacking oxygen. In addition, a method of annealing a substrate comprising a trench containing a dielectric material, the method including annealing the substrate at a first temperature of about 400° C. to about 800° C. in the presence of an oxygen containing gas, purging the oxygen containing gas away from the substrate, and raising the substrate to a second temperature from about 900° C. to about 1100° C. to further anneal the substrate in an atmosphere that lacks oxygen.

Abstract: Methods are provided for depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A process gas having a silicon-containing gas, an oxygen-containing gas, and a fluent gas is flowed into the substrate processing chamber. The fluent gas is introduced into the substrate processing chamber at a flow rate of at least 500 sccm. A plasma is formed having an ion density of at least 1011 ions/cm3 from the process gas to deposit a first portion of the silicon oxide film over the substrate and into the gap. Thereafter, the deposited first portion is exposed to an oxygen plasma having at least 1011 ions/cm3. Thereafter, a second portion of the silicon oxide film is deposited over the substrate and into the gap.