Abstract: A high speed, high sensitivity post amplifier as described herein includes a digitally-controlled DC offset cancellation feature. The amplifier circuit is configured to provide DC offset voltage levels in response to a digital control signal, where the digital control signal is generated based upon a data error metric such as bit error rate. The AC signal path and the DC offset adjustment signal path in the amplifier circuit are separated to facilitate operation with normal power supply voltages, and to achieve low power operation.

Abstract: A system and method have been provided for prioritizing queued information packets having a variable number of cells. A simultaneous deficit round robin (DRR) analysis occurs in the course of several selection cycles. Each queue has an associated increment value. The packet lengths in each queue are simultaneously compared to an accumulation total in every selection cycle. If all the packets have lengths greater than their corresponding accumulation totals, each accumulation total is incremented and the selection process is repeated. If one of the information packets has a number of cells less than, or equal to its corresponding accumulation total, it is selected. In case multiple information packets are eligible, a variety of selection criteria can be used to break a tie. For example, the eligible information packet with the highest class of service (COS) can be selected. The information packet is completed transferred before another selection process is begun.

Abstract: An enhanced performance differential output amplifier and differential amplification method are provided. The amplifier comprises a first transistor to accept a single-ended input signal and supply a first output signal, and a second transistor to supply a second output signal, approximately 180 degrees out of phase from the first output signal. A first capacitor is connected between the base of the first transistor and the emitter of the second transistor. A second capacitor is connected between the emitter of the first transistor and first voltage. At least one emitter resistor, but typically two, is connected between the emitters of the first and second transistors, and a current source. The collectors of the first and second transistors are operatively connected to the first voltage, typically through resistors. The current source is connected between the emitter resistors and a second voltage (Vee) having a lower potential than the first voltage.

Abstract: A substrate interface system and method are provided for connecting a coplanar waveguide transmission line to a coaxial connector. The system comprises a substrate having a top surface with a coplanar waveguide having a transmission line interposed between coplanar groundplanes. A housing wall assembly has an aperture and an interior surface adjacent the substrate coplanar waveguide. A coaxial connector, mounted in the housing wall assembly through the aperture, has a center conductor connected to the coplanar waveguide transmission line and a ground connected to the housing wall assembly. Extensions are mounted on the wall assembly interior surface, connected to the coplanar waveguide groundplanes. The substrate need not be grounded to the coaxial connector through a substrate bottom surface groundplane/chassis interface.

Abstract: A system and method are provided for measuring amplifier gain in a digital network. The method includes accepting a digital input signal; amplifying the input signal (Vin); comparing the amplified signal to dc thresholds; measuring output errors; and, calculating the amplifier gain in response to the thresholds. More specifically, accepting a digital input signal includes accepting an input signal having an amplitude. Comparing the amplified signal to dc thresholds includes comparing the amplified signal to a low threshold and a high threshold. Measuring errors includes measuring a predetermined error condition in response to the high threshold and the low threshold. Then, calculating the amplifier gain in response to the thresholds includes calculating the amplifier gain in response to the high threshold, the low threshold, and the input signal amplitude.

Abstract: A liquid metal socket test fixture system and a method for the same are provided. The system has a circuit board top surface and a plurality of wells. A liquid metal compound forms balls in the wells. An IC package having a bottom surface with electrical contacts interfaces with the liquid metal compound in the wells. In some aspects of the system, the IC package has solid ball grid array (BGA) connectors attached to the bottom surface electrical contacts, interfacing with the liquid metal compound. Alternately, the liquid metal compound interfaces directly to the IC package bottom surface contacts. A gravity-tension frame overlies the circuit board top surface. The frame provides support in the horizontal plane so that the liquid metal balls remain aligned with the IC package electrical contacts. Typically, the liquid metal compound is a mixture of approximately 24% indium and 76% gallium.

Abstract: A high bandwidth emitter-coupled logic (ECL) circuit is provided. The ECL circuit comprises an emitter-follower circuit with first and second transistors having collectors connected to a first power supply (Vcc), and emitters operatively connected to a second power supply (Vee2) approximately 1.5 volts less than the first power supply. The transistors receive differential input signals from an interfacing CML circuit. In some aspects, the first power supply is 3.3 volts and the second power supply is 1.8 volts. The CML circuit has an input to receive an input signal, a logic function having a level of series gated logic, first and second differential output signals responsive to the input signal and logic function, and is powered by the first power supply and a third power supply (Vee3) that is approximately equal to Vcc−(0.4+(level of series gated logic)(0.9 volts)).

Abstract: A system and method are provided for reducing the threshold bias offset voltage in a comparator, by canceling and bypassing the bias offset current errors. The comparator system comprises amplification stages with bias cancellation circuitry and a threshold setting circuit. The bias offset current cancellation circuit is used to cancel the base current of differential amplifier input emitter follower. The bias offset current cancellation circuit also cancels the loading effect of amplifier input emitter-follower driving stage. The threshold offset voltage is further reduced by the threshold setting circuit. The threshold-setting circuit includes two integrators and a unit gain operation amplifier. The integrators have the input accept a single-ended input signal, an output connected to the negative input of the comparator, and an output connected to the unit gain operational amplifier, whose output is connected to the negative input of the comparator.