Abstract: The present invention provides a method for forming a three-dimensional wafer stack having a single metallized stack via with a variable cross-sectional shape. The method uses at least first and silicon wafers. Each wafer has one or more integrated circuits formed thereon. One or more through-vias are formed in each silicon wafer followed by oxide formation on at least an upper and lower surface of the silicon wafer. The wafers are aligned such that each wafer through via is aligned with a corresponding through via in adjacent stacked wafers. Wafers are bonded to form a three-dimensional wafer stack having one or more stack vias formed from the alignment of individual wafer vias. Via metallization is performed by depositing a seed layer in each of the stack vias followed by copper electroplating to form a continuous and homogeneous metallization path through the three-dimensional wafer stack.

Abstract: A method of fabricating a compound semiconductor vertical LED is provided. A first growth substrate capable of supporting compound semiconductor epitaxial growth thereon is provided. One or more epitaxial layers of compound semiconductor material such as GaN or InGaN is formed on the first growth substrate to create a portion of a vertical light emitting diode. Plural trenches are formed in the compound semiconductor material. Passivating material is deposited in one or more trenches. A hard material is at least partially deposited in the trenches and optionally on portions of the compound semiconductor material. The hard material has a hardness greater than the hardness of the compound semiconductor. A metal layer is deposited over the compound semiconductor material followed by metal planarization. A new host substrate is bonded to the metal layer and the first growth substrate is removed. Dicing is used to form individual LED devices.

Abstract: The subject matter disclosed herein relates to an optical emitter-detector for physiological measurements.

Abstract: A method for packing data over a power line communication channel is disclosed herein. The method comprises packing data into symbol body, adding a first pad in front of the symbol body to form a full symbol and determining the time instance in which the peak absolute voltage point of the AC electric power occurs. And subsequently it is to send the full symbol through the power line in a manner synchronized with the time instance aforesaid. Based on the interference condition detection, the invention allows receiver side adaptation.

Abstract: High optical efficiency CMOS image sensors capable of sustaining pixel sizes less than 1.2 microns are provided. Due to high photodiode fill factors and efficient optical isolation, microlenses are unnecessary. Each sensor includes plural imaging pixels having a photodiode structure on a semiconductor substrate adjacent a light-incident upper surface of the image sensor. An optical isolation grid surrounds each photodiode structure and defines the pixel boundary. The optical isolation grid extends to a depth of at least the thickness of the photodiode structure and prevents incident light from penetrating through the incident pixel to an adjacent pixel. A positive diffusion plug vertically extends through a portion of the photodiode structure. A negative diffusion plug vertically extends into the semiconductor substrate for transferring charge generated in the photodiode to a charge collecting region within the semiconductor substrate.

Abstract: A method of making quasi-vertical light emitting devices includes growing semiconductor layers on a growth substrate and etching the semiconductor layers to produce device isolation trenches forming separable semiconductor devices and holes. Blind holes are drilled in the substrate at the location of each of the holes in the semiconductor layers. The drilling of the blind holes defines blind hole walls and a blind hole end in each of the blind holes. N-semiconductor metal is deposited in each of the blind holes. An n-electrode contact is formed in each of the blind holes by plating each of the blind holes with an n-electrode metal connected to the n-semiconductor metal. The substrate is thinned to expose the n-electrode metal as an n-electrode. Bonding metal is deposited to the n-electrode for packaging.

Abstract: Thermal inkjet printer sublimation inks are provided having high melting point suspended particles such that the ink does not clog thermal ink jet print heads. Low-cost thermal ink jet printers are used to create thermal transfer images from the inks which are used in conventional thermal transfer processes. An ink set having at least three ink colors includes an aqueous medium of 30-95 weight percent having particles of 50 nm to 1000 nm suspended therein in an amount of 1-10 weight percent. The suspended particles include a sublimation dye and have a melting point of at least a surface of the particle greater than or equal to 200° C. The particles may have a core-shell structure with a sublimation dye core. The ink includes one or more cosolvents from 4-40 weight percent, a surfactant of 0.01 to 5 weight percent, and a biocide of 0.01-5 weight percent.

Abstract: A method of increasing the dynamic range of an image comprising a plurality of pixels each having a luminance value within a first luminance dynamic range. The method includes determining a background luminance value for each pixel of the image and determining a minimum and a maximum of the background luminance values. A conversion factor is then determined for each pixel of the image based on the minimum and maximum of the background luminance values. The image id converted from the first luminance dynamic range to a second luminance dynamic range by multiplying the luminance value of each pixel of the image by its conversion factor.

Abstract: An integrated circuit modeling method 100 implementable on computer, which has an executable software model 145 having modules 140 of reusable functional cores 105 coded in a high level language and a virtual platform of the integrated circuit employable in an architecture exploration step 115. A modeling library of modules coded in high level languages and hardware level languages are provided and instantiated according to user input in a functional verification step 120 having a co-simulation environment, with interface code 170 between modules automatically generated by an interface generator 130 based on a two dimensional data array of hardware specification inputs 205, the interface code 170 further interfacing with wrappers engaged between high and hardware level language modules.

Abstract: The present invention relates to a method of channel estimation comprising two major steps. The first step is the least-squared and minimum mean-square error (MMSE) estimations on the pilot resource elements to generate the channel response estimates at the predefined pilot locations. The second step of the channel estimation, which utilizes the results from the first step to compute the channel response estimates for the remaining resource elements, comprises the following three operations: (i) averaging of each pair of adjacent pilot resource elements in the frequency direction to obtain the channel response estimate of the resource element in the middle of those two pilot resource elements; (ii) MMSE interpolation in the time domain for all the sub-carriers containing pilot signals; and (iii) linear interpolation in the frequency direction for all the sub-carriers not containing any pilot signals.

Abstract: One aspect of the present invention provides an electronic package, comprising at least a first module and a second module arranged on top of the first module, the modules together in the form of a module stack, wherein the first and second modules are adhesively connected together, each module includes a substrate layer having at least one metal layer, at least one die and a plastic(s) package molding compound layer molded over said die or dice, in each module the die or dice are bonded on said substrate layer via the metal layer, a plurality of channels formed generally vertically acting as vias to connect the metal layers and arranged adjacent to the die or dice in at least one of the modules, some or all the channels provided with an inner surface coated with a conductive material layer or filled with a conductive material for electrical connection whereby the dice are electrically connected together, and means serving as an intermediary for providing electrical, mechanical and thermal connectivity, commu

Abstract: A bandgap reference circuit has trimming-up resistors and trimming-down resistors for bi-directional trimming. PNP transistors have base and collectors grounded and emitters connected to parallel resistors. A difference resistor drives an inverting input of an op amp that drives a transistor that generates the bandgap reference voltage Vbg. A sensing resistor connects Vbg to a splitting node that connects to the non-inverting input through a first parallel resistor. The splitting node also connects through a second parallel resistor to the inverting input. Fuses or switches enable the trimming-up and trimming-down resistors. The trimming-up resistors are in series with the sensing resistor and the trimming-down resistors are in series with an output resistor that connects Vbg to reference voltage Vref. The circuit can be designed for a more typical process since bi-directional trimming allows Vref to be raised or lowered. Many circuits need no trimming when targeted for the typical process.

Abstract: The present invention relates to a printhead for thermal inkjet printing and the printing method thereof. The printhead includes: a substrate having a plurality of orifices with a firing element in each of said plurality of orifices, wherein said plurality of orifices are arranged in a single column, and said printhead is disposed at an angle to a horizontal direction along which said printhead scans; and firing circuits for energizing said plurality of firing elements to eject ink on a printing medium by respectively transmitting a plurality of firing signals to said plurality of firing elements. According to the present invention, the print speed and resolution can be improved.

Abstract: The present invention provides a method of fabricating vertical LED structures in which the substrate used for epitaxial layer growth is removed through polishing. The polishing technique used in an exemplary embodiment is chemical mechanical polishing using polish stops to provide a sufficiently level plane. Polish stops are provided in the multilayer structure before polishing the surface, the hardness of the polish stop material being greater than the hardness of the material that needs to be removed. Consequently, vertical LEDs can be produced at a lower cost and higher yield compared to either laser lift-off or conventional polishing. Exemplary vertical LEDs are GaN LEDs. The polish stops may be removed by saw dicing, laser dicing or plasma etching.

Abstract: A valve for a tire pressure monitoring system in which the valve acts a coaxial conductor to transmit a signal to a receiver presented. A valve stem electrically isolated from a valve pin form the coaxial conductor. In a tire pressure monitoring system, a tire pressure measurement module is positioned inside a tire. In one embodiment, a conductive radiating structure is electrically connected or coupled to the valve pin to receive the tire pressure information signal and transmit it to a receiver. The above configuration further permits a rechargeable battery in the tire pressure measurement module to be recharged via the tire valve. The valve pin and valve stem, being electrically isolated from one another, are used as recharging paths for the battery.

Abstract: A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC.

Abstract: A motor driver circuit for driving the gate node of a high-side driver transistor to a boosted voltage from a charge pump draws little or no static current from the charge pump. The gate node is pulled to the boosted voltage by a p-channel pullup-control transistor that is driven by p-channel transistors that are pumped by capacitors that cut off current flow to ground from the charge pump. An n-channel output-shorting transistor shorts the gate node to the output when the high-side driver is turned off. A coupling capacitor initializes the shorting transistor for each output transition. A p-channel output-sensing transistor generates a feedback to a second stage that drives the coupling capacitor. P-channel diode transistors and an n-channel equalizing transistor control the voltage on the coupling capacitor.

Abstract: A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC.

Abstract: A method includes receiving encoded media content, transforming the encoded media content into web page content by dividing the encoded media content into a plurality of web page files formatted as a static web page, and transmitting the web page content over the network in response to a request.

Abstract: A content distribution method with broadcast encryption, comprising an encryption process that includes the computation of a ciphertext using a differential ciphertext generation method. The ciphertext needs to be recomputed whenever the subscriber set changes. The differential ciphertext generation method computes the new ciphertext by reusing previously preserved computational results of a previous ciphertext, thereby improving the efficiency of the system. A content distribution method with broadcast encryption also comprises a decryption process that includes the reconstruction of the encryption secret that is used for decrypting the encrypted content. A wide window point addition method is used in the encryption secret reconstruction. The wide window point addition method reuses previously preserved computational results of group-divided point additions of public parameters, thereby improving the efficiency of the system.