Abstract: Substrate supports comprising a plurality of bonded plates forming a single component support body and methods of forming the substrate supports are described. The single component support body has an outer peripheral edge, a top surface and a bottom surface. A pocket is formed in the top surface and has a bottom surface, a depth and an outer peripheral edge. A purge ring is spaced a distance from the outer peripheral edge and comprises at least one opening in the top surface in fluid communication with a purge gas line within the body thickness.
Abstract: Embodiments of the disclosure generally provide methods of using an interface protection layer disposed between an active layer and a source-drain metal electrode layer. In one embodiment, a method for forming an interface protection layer in a thin film transistor includes providing a substrate having an active layer formed thereon, wherein the active layer is a metal oxide layer, forming an interface protection layer on a portion of the active layer, and forming a source-drain electrode layer on the interface protection layer.
Abstract: Methods of forming a dielectric layer where the tensile stress of the layer is increased by a plasma treatment at an elevated position are described. In one embodiment, oxide and nitride layers are deposited on a substrate and patterned to form an opening. A trench is etched into the substrate. The substrate is transferred into a chamber suitable for dielectric deposition. A dielectric layer is deposited over the substrate, filling the trench and covering mesa regions adjacent to the trench. The substrate is raised to an elevated position above the substrate support and exposed to a plasma which increases the tensile stress of the substrate. The substrate is removed from the dielectric deposition chamber, and portions of the dielectric layer are removed so that the dielectric layer is even with the topmost portion of the nitride layer. The nitride and pad oxide layers are removed to form the STI structure.
October 15, 2008
February 5, 2009
Applies Materials, Inc.
Xiaolin Chen, Srinivas D. Nemani, DongQing Li, Jeffrey C. Munro, Marlon E. Menezes
Abstract: A method for adjusting a spacing of a leveling plate from a chamber body comprises attaching a mounting stud that includes a stud threaded surface to the chamber body. An adjustment screw is provided that has a first threaded surface threadingly engaged with the stud threaded surface. A bushing is provided that has a bushing threaded surface threadingly engaged with a second threaded surface of the adjustment screw. The bushing is movably coupled to the leveling plate. Coarse adjustment of the spacing between the leveling plate and the chamber body is made by rotating the adjustment screw with respect to the mounting stud. The bushing is fixed to the leveling plate. Fine adjustment of the spacing between the leveling plate and the chamber body is made by rotating the adjustment screw with respect to the mounting stud and the bushing.
Abstract: A method for depositing a low dielectric constant film is provided by reacting a gas mixture including one or more linear, oxygen-free organosilicon compounds, one or more oxygen-free hydrocarbon compounds comprising one ring and one or two carbon-carbon double bonds in the ring, and one or more oxidizing gases. Optionally, the low dielectric constant film is post-treated after it is deposited. In one aspect, the post treatment is an electron beam treatment.
February 4, 2004
Date of Patent:
June 6, 2006
Applies Materials Inc.
Kang Sub Yim, Yi Zheng, Srinivas D. Nemani, Li-Qun Xia, Eric P. Hollar
Abstract: A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon. In one embodiment the method includes depositing a first hard mask layer over the dielectric layer and depositing a second hard mask layer on the first hard mask layer, where the second hard mask layer is an amorphous silicon layer. Afterwards, formation of the dual damascene structure is completed by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material.
March 18, 2002
September 18, 2003
Applies Materials, Inc.
Timothy Weidman, Nikolaos Bekiaris, Josephine Chang, Phong H. Nguyen
Abstract: A sputtering hybrid coil for a plasma chamber in a semiconductor fabrication has an enhanced sputtering surface and an internal coolant carrying channel thermally coupled to the sputtering surface to cool the sputtering surface and the coil.