Patents Assigned to APRESIA Systems, Ltd.
  • Patent number: 10298520
    Abstract: A relay apparatus includes line cards, switch fabric cards, and a management card. The management card and the switch fabric cards are connected through a first communication network, and the switch fabric cards and the line cards are connected through a second communication network. The switch fabric card includes an error control unit. The error control unit stops switching of data transmission using a path of the second communication network by controlling the switch fabric card as an abnormal state based on an error signal that is output when a fault of the first communication network or an internal fault of the switch fabric card is detected as an error.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: May 21, 2019
    Assignee: APRESIA Systems, Ltd.
    Inventors: Muneyuki Ikarashi, Shigeru Tsubota
  • Patent number: 10256990
    Abstract: A plurality of management cards including an active card and a standby card are provided. The active card determines open or block of a ring port in accordance with an event based on a ring protocol, issues an open instruction or a block instruction to a line card, and notifies a block factor in addition to the block instruction when issuing the block instruction. The line card controls open or block of the ring port in accordance with the open instruction or the block instruction and retains open/block information of the ring port and a block factor of the block state in a port management table. When the standby card is changed to the active card in accordance with a predetermined change instruction, it acquires the information retained in the port management table from the line card.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 9, 2019
    Assignee: APRESIA Systems, Ltd.
    Inventor: Makoto Yasuda
  • Patent number: 10171259
    Abstract: A network system includes: a VXLAN region that is connected to a vEPC virtual network and in which encapsulation by VXLAN is performed; a PBB region in which encapsulation by PBB is performed; an edge router that belongs to the VXLAN region and is connected to an edge switch in the PBB region; and an edge switch that belongs to the PBB region and is connected to the edge router. The edge router performs conversion between a VNID of data encapsulated by the VXLAN and an intermediate CVID of decapsulated data exchanged with the edge switch, and the edge switch performs conversion between an ISID of data encapsulated by the PBB and the intermediate CVID.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: January 1, 2019
    Assignee: APRESIA Systems, Ltd.
    Inventors: Hitoshi Kuwata, Toshihiko Murakami, Tatsuro Matsumoto
  • Publication number: 20180115297
    Abstract: A phase-shifting circuit 1 includes a signal conductor 2 that transmits signals, and a dielectric body 3 that is disposed to overlap the signal conductor 2, said phase-shifting circuit changing the phase of the signals by changing the area of an overlapping section 5 where the signal conductor 2 and the dielectric body 3 overlap each other. The phase-shifting circuit further includes a transformer unit 7 for matching impedance between the overlapping section 5 and non-overlapping section 6 where the signal conductor 2 and the dielectric body 3 do not overlap each other, said transformer unit being provided at end sections of the dielectric body 3, said end sections being on the input side and output side of the signals.
    Type: Application
    Filed: March 30, 2015
    Publication date: April 26, 2018
    Applicant: APRESIA Systems, Ltd.
    Inventors: Satoshi YOSHIHARA, Seiji KADO, Nobuaki KITANO
  • Patent number: 9948447
    Abstract: Provided is a communication apparatus usable for any case where a time synchronization function is necessary or unnecessary by attaching or detaching a synchronization model for realizing the time synchronization function. A clock generation unit, a logic circuit unit including a synchronization module monitoring unit, a clock selection unit, and a main circuit unit configured by a switch LSI are integrally formed on the same substrate, and the synchronization module is detachably mounted on the substrate via connectors. The connectors each have a mounting determination pin that indicates a different signal level depending on whether the synchronization module is mounted. The synchronization module monitoring unit monitors connection signals indicating signal levels of the mounting determination pin, and causes the clock selection unit to select a synchronization clock when the synchronization module is mounted, and an internal clock when the synchronization module is not mounted.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: April 17, 2018
    Assignee: APRESIA Systems, Ltd.
    Inventor: Daisuke Fujiu
  • Publication number: 20180013186
    Abstract: A phase shifter includes a signal conductor constituting a transmission line for a signal transmitted through an antenna element, a dielectric plate including a dielectric material disposed to face to the signal conductor, and a mobile mechanism for moving the dielectric plate. A facing area between the signal conductor and the dielectric plate is changed by a movement of the dielectric plate, to change a phase of the signal transmitted through the signal conductor. The dielectric plate includes a transformer unit for impedance matching between an overlapped portion in which the signal conductor faces to the dielectric plate and a non-overlapped portion in which the signal conductor does not face to the dielectric plate.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 11, 2018
    Applicant: APRESIA Systems, Ltd.
    Inventors: Shinsuke MURANO, Ryoji MATSUBARA, Kei KAWANO