Abstract: A data transfer system with improved data transfer efficiency is provided. The system consists of a data interchange bus having two data transfer signal paths, an address signal path, and a plurality of control signal paths. Data interchange adapters and memory interchange adapters are coupled to the bus for transferring data thereover. A data interchange adapter transfers data on the first data signal path to another data interchange adapter or to a memory interchange adapter for storage in a memory device. A memory interchange adapter transfers data obtained from a memory device on the second data signal path to a data interchange adapter. Data transfers on the two data signal paths may be made simultaneously. Data transfers on both data signal paths are made synchronously.

Abstract: A high performance interleaved memory addressing system and method. A plurality of banks of random access memory devices are provided. The appropriate bank for a given memory address is selected based upon the parity among a preselected set of address bits including the least significant bit. A parity signal for selection of a memory bank is produced by a parity signal generation circuit, preferably a logic circuit. Typically, more than two memory banks would be employed, utilizing at least two parity signal generation circuits, each corresponding to respective least significant bits of the memory address. The output signals from the parity circuits are combined in a decoder to select the memory bank.