Abstract: A field programmable printed circuit board is provided which includes a multiplicity of component contacts for making electrical contact to the leads of electronic components to be mounted on the printed circuit board, a corresponding multiplicity of interconnect contacts for receipt of the leads on the package or packages of a programmable integrated circuit or circuits for interconnecting as desired the electronic components, and one or more layers of conductive traces formed on the printed circuit board, each conductive trace uniquely connecting electrically one component contact to one interconnect contact.

Abstract: An interconnect structure is centered around a substrate having opposite first and second surfaces. Component contacts allocated to cells in the substrate, are provided over both substrate surfaces. Conductive leads extend over each surface in two different directions. The conductive leads are selectively connected to the component contacts. The interconnect structure includes a capability for programmability electrically connecting, or disconnecting, the conductive leads in a desired manner.

Abstract: An interconnect structure is centered around a substrate having multiple component contacts for receiving electronic components. Multiple conductive traces are provided over the substrate or in multiple layers of the substrate. Each conductive trace is connected to one of the component contacts. A programmable IC having a group of separate conductive leads is connected to the substrate. Two or more of the conductive leads are connected to corresponding ones of the conductive traces. The IC has programmable elements, such as electrically programmable elements, for selectively connecting the conductive leads, thereby enabling selected conductive traces to be interconnected so as to achieve a desired electrical function from the electronic components connected to the substrate. A test chip, an interconnect structure that contains the test chip, and a related test method are also provided.

Abstract: A two-terminal fuse-antifuse structure comprises a horizontal B-fuse portion and a vertical A-fuse portion disposed between two metallization layers of an integrated circuit device. The two-terminal fuse-antifuse can be programmed with a relatively high current applied across the two terminals to blow the B-fuse, or with a high voltage applied across the two terminals to program the A-fuse. Such a device, connected between two circuit nodes, initially does not provide an electrical connection between the two circuit nodes. It may then be programmed with a relatively high voltage to blow the A-fuse, causing it to conduct between the two circuit nodes. Then, upon application of a relatively high current between the two circuit nodes, the B-fuse will blow, making the device permanently non-conductive.

Abstract: A field programmable printed circuit board is provided which includes a multiplicity of component contacts for making electrical contact to the leads of electronic components to be mounted on the printed circuit board, a corresponding multiplicity of interconnect contacts for receipt of the leads on the package or packages of a programmable integrated circuit-or circuits for interconnecting as desired the electronic components, and one or more layers of conductive traces formed on the printed circuit board, each conductive trace uniquely connecting electrically one component contact to one interconnect contact.

Abstract: An interconnect structure is centered around a substrate having multiple component contacts for receiving electronic components. Multiple conductive traces are provided on the substrate. Each conductive trace is electrically connected to one of the component contacts. A programmable IC having a group of separate conductive leads is connected to the substrate. Two or more of the conductive leads are connected to corresponding conductive traces on the substrate. The IC has programmable elements for selectively connecting the conductive leads, thereby enabling a user to interconnect selected conductive traces on the substrate to achieve a desired electrical function from the electronic components connected to the substrate. The interconnect structure also contains circuitry for transmitting control signals to the programmable IC to control its configuration so as to control the interconnection of the conductive traces.

Abstract: The invention uses a programmable interconnect substrate having a plurality of conductive and interconnectable vias located on one or both surfaces thereof. A customized pattern of bonding pads is then formed over the one or both surfaces of the substrate which correspond to the terminal footprints of specific surface mounted packages intended to be mounted on the substrate. A generalized pattern of bonding pads may also be formed on the surfaces of the substrate for electrically connecting terminals of bare dice thereto by means of thin wire. All bonding pads are electrically connected to one or more vias by direct electrical contact or by a conductive trace extending from the bonding pad to a nearby via.

Abstract: A structure for interconnecting electronic components contains a group of first programmable integrated circuits (331-1-331-3 and 331-5-331-7), at least one second programmable integrated circuit (331-4) and at least one substrate (300), typically a printed circuit board. The first programmable integrated circuits are connected through conductive traces to component contacts formed on the substrate(s) for receiving the electronic components. The first programmable integrated circuits are also connected through bus lines (333-1-333-3 and 333-5-333-7) to the second programmable integrated circuit(s). The electronic components are thereby interconnected through the combination of the first and second programmable integrated circuits.

Abstract: An interconnect structure contains an interconnect substrate, multiple component contacts formed on the interconnect substrate for receipt of electronic components, and multiple conductive traces formed on the interconnect substrate. Each conductive trace is electrically connected to one of the component contacts. An IC having a group of parallel of conductive leads is mounted on the substrate. At least one of the conductive leads is divided into two or more segments. One or more of the conductive leads or segments are connected to corresponding conductive traces on the interconnect substrate. In one embodiment, the IC is a programmable chip having programmable elements for selectively connecting the conductive leads or segments, thereby enabling a user to interconnect selected conductive traces on the interconnect substrate to achieve a desired electrical function from the electronic components connected to the substrate.

Abstract: A user-programmable interconnect device includes a first lower electrode comprising a conductive material. A layer of dielectric material is disposed over the top surface of the lower conductor. An antifuse material, such as one or more layers of a dielectric material, amorphous silicon, or combinations of such materials, is located in an aperture in the dielectric material where the interconnect element of the present invention is to be formed. A second, upper electrode of conductive material is formed over the top of the antifuse material. A portion of the upper electrode located immediately above the antifuse material is fabricated as a fuse material. A passivation layer covers the second electrode and may have an aperture located therein at a location immediately above the antifuse and fuse material. Electrical connections to circuitry incorporating the interconnect element of the present invention are made to the lower and upper electrodes.

Abstract: A high I/O count integrated circuit is disposed on a semiconductor chip having opposing faces and comprises a plurality of functional circuit modules, each having inputs and at least one output having a first drive capability. A plurality of a first type of I/O nodes, each comprising a first conductive structure is disposed in a first I/O node array on the surface of a first one of the semiconductor chip faces. A plurality of a second type of I/O nodes, each comprising a first conductive structure is disposed on the first semiconductor chip face. An interconnect architecture comprising a plurality of conductors is superimposed on the functional circuit modules, the interconnect architecture comprises a plurality of interconnect conductors. Selected ones of the interconnect conductors are connectable to the inputs and at least one output of selected ones of the functional circuit modules by electrically programmable user-programmable interconnect elements.

Abstract: A programmable interconnect system includes a two-level hierarchal structure of programmable interconnect chips on a circuit board. The first-level, or "local", interconnect chips are connected to user components. A plurality of second-level, or "global", interconnect chips interconnect the local interconnect chips so that every local chip is connected to every global chip. Such a system allows connecting any pin of any user component to any other pin of any user component by a conductive path passing through at most three interconnect chips. A large number of such paths are provided even in embodiments with a large number of interconnect chips.

Abstract: An integrated circuit package for demountable attachment to a printed circuit board or like device is formed from an integrated assembly of an IC chip and socket, The IC chip is permanently mounted to a chip carrier which spreads the contact area from a first area to a larger second area. The chip carrier or spreader is contained in a plastic socket formed of a cover and a base. The base has an array of apertures therethrough each of which is equipped with wadded wire/plunger contacts for conformal contact with both pads on the bottom of the chip carrier and pads on a circuit board.

Abstract: An interconnection matrix configured according to the present invention includes a plurality of conductors disposed on a substrate which may contain an integrated circuit. A first group of the conductors are directly connected to I/O pins provided on the substrate. A second group of the conductors are internal to the substrate. A plurality of programmable elements are disposed on the substrate and are connected between selected ones of the first and second groups of conductors. By selectively programming the antifuse elements, a user may configure the conductors into a custom interconnect pattern. Means are provided to place each conductor in the second group of internal segmented conductors at a selected voltage during programming of the interconnect architecture of the present invention. The antifuses in a selected circuit path between two I/O pads are all initially programmed at an appropriate programming voltage utilizing a low current.

Abstract: A first user re-programmable interconnect architecture is provided wherein N switching elements are connected between selected interconnect conductors. The switching elements are controlled by M active storage elements, where M<N. A group of N switching elements are controlled by a group of M active storage elements, where M<N. The states of the M active storage elements are collectively decoded to identify the one of N switching elements to be turned on. A second user re-programmable interconnect architecture is provided wherein a group of N switching elements are connected between selected interconnect conductors and are partially selected by decoding the states of m.sub.1 active storage elements. The group of N switching elements are also partially selected by decoding the states of m.sub.2 active storage elements. The decoding is arranged such that the states of m.sub.1 and m.sub.

Abstract: A method for fabricating a printed circuit board for high pin count surface mount pin grid arrays is provided where surface mount pads for soldering a surface mount pin grid array package are isolated by solder mask layers. The printed circuit board is laminated with one or more solder mask layers containing apertures therein to expose the surface mount pad locations.

Abstract: A universal interconnect matrix area array or crosspoint switch is comprised of a first set of conductive leads formed in a first direction, a second set of conductive leads formed in a second direction, the second direction being not parallel to the first direction, and structure for electrically interconnecting selected ones of the conductive leads in the first set of conductive leads to one or more of the conductive leads in the second set of conductive leads. Input/output pads are arranged in an area matrix and connected to selected ones of the first set of conductive leads and the second set of conductive leads. Selected ones of the conductive leads are segmented thereby to allow any input/output pad to be connected to one or more of the other input/output pads without removing from use any input/output pads not intended to be so connected. At least one of the input/output pads is internal to the input/output pads along the periphery of the area matrix.

Abstract: Apparatus for forcing a memory cell to a user-selected logic level upon power-up includes circuitry for providing two signals PWRUP and PWRUPB which are used during chip power-up. At power-up, as V.sub.CC rises from 0 volt to 3.5 volts, the PWRUP signal follows V.sub.CC and the PWRUPB signal maintains 0 volts. The PWRUP and PWRUPB signals are used to drive the gates of P-Channel and N-Channel MOS transistors, respectively, including pass gates connected between word line driver circuits and bit line driver circuits driving the word lines and bit lines associated with the memory cells. In addition, the PWRUPB signal is used to drive P-Channel MOS pullup transistors connected between the word lines and V.sub.CC and bit lines and V.sub.CC. During power-up, the pass gates are disabled, disconnecting the word lines and bit lines from their drivers. The word lines and bit lines are forced to follow the rise of V.sub.CC by the P-Channel pullup transistors. When V.sub.

Abstract: A printed circuit board includes an array of conductive pads including component-mounting holes disposed on first and second surfaces thereon. An array of conductive attachment lands arranged in pairs of first and second attachment lands are disposed on the first and second surfaces. The first and second attachment lands are insulated from one another and separated by a distance selected to allow attachment of standard sized components therebetween on the first and second surfaces of said circuit board. First and second conductive power distribution planes are disposed on the first and second surfaces and are insulated from the conductive pads and the second attachment lands disposed thereon.

Abstract: A package for one or more integrated circuit dice which includes a spreader which provides a conventional signal path between the die and a printed circuit board to which it is demountably attached as well as an additional, more readily accessible subset of signals, preferably available through a flexible cable extending horizontally from the package. The spreader provides a first set of contacts on a first side for interface to the integrated circuit dice, a second set of contacts on a second side opposite the first side which are connected to some of the contacts of the first set of contacts for connection to the printed circuit board, and a third set of contacts on the first side along one edge thereof for engaging the flexible cable and carrying the subset of signals.