Abstract: In one implementation, a decoding architecture is provided that includes an input buffer configured to receive and store one or more codewords to be processed, and a decoder coupled to the input buffer. The decoder is configured to receive a first codeword and a second codeword from the input buffer, and simultaneously process the first codeword and the second codeword such that each of the first codeword and the second codeword is processed only for a minimum amount of time for the first codeword or the second codeword to become decoded. The input buffer is further configured to load a third codeword into the decoder responsive to the first codeword or the second codeword being decoded.

Abstract: Trapping set decoding for transmission frames is disclosed. In one aspect, a trapping set decoder includes a detector including an input to receive a decoded codeword and including circuitry to detect the presence of one or more trapping sets of bits in the decoded codeword. A selection processor is coupled to the detector to select one from a group of trapping sets and correct one or more bits in the decoded codeword based on statistical measures associated with the one or more trapping sets of bits.

Abstract: Low-power idle mode for network transceivers. In one aspect, a method for reducing power consumption of a transceiver connected to a communication network includes entering a low-power idle mode, and in this mode, repeatedly turning off a transmitter of the transceiver and turning on the transmitter according to a pattern, where the pattern has been customized based on characteristics of the receiver. Turning off the transmitter conserves power consumed by the transceiver.

Abstract: Compensation of transmit baseline wander in data transmission on a network. In one aspect, compensating for baseline wander includes receiving a signal to be transmitted by a transmitter, where the transmitter is operable with a higher-speed transmission standard requiring magnetics a first open circuit inductance. The signal is processed to compensate for a transmit baseline wander in the signal, the transmit baseline wander associated with a lower-speed transmission standard that requires magnetics with a second open circuit inductance that is higher than the first open circuit inductance. The processed signal is to be provided for transmission on a twisted pair cable of the network.

Abstract: Trapping set decoding for transmission frames is disclosed. In one aspect, a trapping set decoder includes a decoder that performs decoding operations on an encoded codeword in received data, and a detector coupled to the decoder for detecting the presence of any one of a group of possible trapping sets in the decoding operations on the encoded codeword. A selection processor is also included, coupled to the decoder, for providing a decoded codeword by selecting one trapping set of the group of possible trapping sets, the selected trapping set being present in the decoding operations of the codeword, and by using the selected trapping set to produce the decoded codeword.

Abstract: A decoder and method for implementing an iterative error correcting decoder are provided for decoding a codeword consisting of a N-bit messages. In one implementation, the decoder includes a first set of nodes, and a second set of nodes, each having N bits of resolution. Each node of the second set is coupled to at least one node of the first set, each node of the second set being coupled to a node of the first set by a corresponding set of M wires. Each of the first set of nodes is operable to transfer the bits of a given N-bit message of the codeword over the corresponding set of M wires to a coupled node of the second set during a single iteration cycle, each of the M wires carrying i bits, where N is an integer greater than M, and N=M*i.

Abstract: A decoder architecture and method for processing codewords are provided. In one implementation, the decoder architecture includes an input buffer configured to receive and store one or more codewords to be processed, and a decoder configured to receive codewords one at a time from the input buffer. The decoder processes each codeword only for a minimum amount of time for the codeword to become error free. The decoder architecture further includes an input buffer monitor and supply regulator configured to change a voltage supply to the decoder responsive to an average amount of time or each codeword to become error free.

Abstract: An iterative error correcting decoder is provided. In one implementation, the iterative error correcting decoder includes an equality constraint node and a parity check node, the parity check node. The parity check node includes parity logic configured to receive input data bits from the equality constraint node and determine a first minimum value and a second minimum value associated with the input data bits using a MinSum algorithm. An enhancement function is performed on the first minimum value and the second minimum value. The enhancement function compares each of the first minimum value and the second minimum value with a first pre-determined constant value, and responsive to the first minimum value and the second minimum value being smaller than the first pre-determined constant value, the enhancement function passes the first minimum value and the second minimum value without any changes as output of the MinSum algorithm.

Abstract: A method and system for determining low error rate behavior of a device are provided. In one implementation, the method includes obtaining a dominant trapping set of a code, the dominant trapping set containing a plurality of variable nodes, and biasing bits associated with a programmable transmitter that is in communication with the device. The biased bits correspond to the variable nodes of the dominant trapping set. The method further includes transmitting random data from the programmable transmitter to the device, in which the random data includes one or more of the biased bits; measuring a number of error events corresponding to biased bits received by the device that cannot be decoded; and determining a true bit error rate of the device based on the measured number of error events.

Abstract: Methods and systems for cancelling interference in an analog communication signal are provided. The method includes receiving an analog communication signal including interference caused by a deterministic interference source, generating a digital interference signal corresponding to the interference caused by the deterministic interference source, converting the digital interference signal into a corresponding analog interference signal, and subtracting the analog interference signal from the analog communication signal.

Abstract: A digital-to-analog converter (DAC) configured to operate in high frequency and/or high resolution environments. The DAC has a segmented architecture comprising one or more least significant bit (LSB) thermometer sub-converters and one or more most significant bit (MSB) thermometer sub-converters. A binary converter can also be added. The LSB and MSB thermometer sub-converters include cell pairs with a main cell and a dummy cell. The main cell switches according to actual data, drawing power from a voltage source at each transition. To maintain a consistent voltage level at the output, the dummy cell creates a transition to draw power from the voltage source responsive to a lack of transition in the main cell. Each cell pair has a dedicated voltage source. Also, the MSB thermometer sub-converter can include a load matching circuit to match the parasitic capacitance of the LSB thermometer sub-converter at an output.

Abstract: Described are an iterative decoder and method for implementing an iterative decoder which can be used for error correction in data communications. In one implementation, the method includes implementing a first function including a first plurality of Gilbert cells, and implementing a second function including a second plurality of Gilbert cells, where examples of the first and second functions include an equality constraint function and a parity check function. Each of the first plurality of Gilbert cells and the second plurality of Gilbert cells includes n m-input Gilbert multipliers, in which n is an integer greater than (3) and m=(n?1).

Abstract: A circuit is provided that (in one implementation) includes a first transistor having a first drain terminal, first gate terminal, and a first source terminal. The first drain terminal is connected to the first gate terminal, the first source terminal is connected to a first voltage. The circuit further includes a second transistor having a second drain terminal, second gate terminal, and a second source terminal. The second gate terminal is connected to both the first gate terminal and the first drain terminal, and the second source terminal is connected to the first voltage. The circuit further includes a third transistor having a third drain terminal, a third gate terminal, and a third source terminal. The third drain terminal is connected to the first drain terminal, and the third source terminal is connected to both the third gate terminal and a second voltage that is lower than the first voltage.

Abstract: Low-power idle mode for network transceivers. In one aspect, a method for reducing power consumption of a transceiver connected to a communication network includes entering a low-power idle mode, and in this mode, repeatedly turning off a transmitter of the transceiver and turning on the transmitter according to a pattern, where the pattern has been customized based on characteristics of the receiver. Turning off the transmitter conserves power consumed by the transceiver.

Abstract: A circuit is provided that includes a current source, and a compensation circuit to generate a compensation current based on an output voltage of the current source. The circuit further includes a combiner to combine the compensation current with an output current of the current source to substantially cancel a channel-length modulation effect associated with the output current of the current source.

Abstract: A signal processing system includes an AGC and pre-echo cancellation system for receiving an analog signal, amplifying signal magnitude (over all frequencies) to a pre-determined level by AGC, and removing the immediate transmit pulse from this received signal by pre-echo canceller to provide a second analog signal. The signal processing system also includes a summer for receiving the analog signal; a feed forward equalization (FFE) unit for receiving a signal from the summer; and a slicer for receiving a signal from the FFE unit and providing an output signal. The signal processing system also includes an Echo and NEXT or FEXT cancellation system for receiving the output signal and for providing a signal to the summer for canceling the echo and crosstalk in the signal processing system. The Echo and crosstalk components associated with a signal processing system can be subtracted prior to the FFE.

Abstract: A decoder architecture and method for implementing a decoder are provided. In one implementation, the decoder architecture includes an input buffer configured to receive a plurality of codewords to be processed, and includes an iterative decoder configured to receive a first codeword from the input buffer and process the first codeword. The iterative decoder processes the first codeword only for an amount of time required for the first codeword to become substantially error free. The decoder architecture further includes logic coupled to each of the iterative decoder and the input buffer. The logic is configured to determine when the first codeword processed by the decoder becomes substantially error free. The logic further generates a signal for loading a second codeword from the input buffer into the iterative decoder responsive to the logic determining when the first codeword becomes substantially error free.

Abstract: Trapping set decoding for transmission frames is disclosed. In one aspect, a trapping set decoder includes a decoder that performs decoding operations on an encoded codeword in received data, and a detector coupled to the decoder for detecting the presence of any one of a group of possible trapping sets in the decoding operations on the encoded codeword. A selection processor is also included, coupled to the decoder, for providing a decoded codeword by selecting one trapping set of the group of possible trapping sets, the selected trapping set being present in the decoding operations of the codeword, and by using the selected trapping set to produce the decoded codeword.

Abstract: The line driver circuit is provided that includes a first pull-up variable resistor connected between a first power supply and the first output terminal, a second pull-up variable resistor connected between the first power supply and the second output terminal, a first pull-down variable resistor connected between a second power supply and the first output terminal, a second pull-down variable resistor connected between the second power supply and the second output terminal, a floating variable resistor connected between the first output terminal and the second output terminal, and coder logic to adjust an output voltage across the first output terminal and the second output terminal by varying a resistance of one or more of the floating variable resistor, the first pull-up variable resistor, the second pull-up variable resistor, the first pull-down variable resistor, and the second pull-down variable resistor in response to received data bits.

Abstract: A low-power multi-level pulse amplitude modulation (PAM) line driver using variable resistors for transmitting digital data over controlled-impedance transmission lines.