Abstract: The present invention relates to a process for the wet production of granules from powdered materials, in particular raw materials for the production of glass. The process of the invention comprises the following successive steps: (i) the powdered materials to be granulated are divided into at least two portions: a first portion and a second portion; (ii) a binder liquid is added to the first portion of powdered materials; (iii) the first mixture thus obtained is agglomerated in the granulator in order to obtain granules (a); (iv) the second portion of powdered materials is added to the granulator; and (v) the new mixture obtained is agglomerated in the granulator in order to obtain granules (b). This sequenced granulation process allows granules to be obtained that have a degree of moisture that assures their stability and their ease of handling eliminating the drying step.

Abstract: The present invention relates to a process for the wet production of granules from powdered materials, in particular raw materials for the production of glass. The process of the invention comprises the following successive steps: (i) the powdered materials to be granulated are divided into at least two portions: a first portion and a second portion; (ii) a binder liquid is added to the first portion of powdered materials; (iii) the first mixture thus obtained is agglomerated in the granulator in order to obtain granules (a); (iv) the second portion of powdered materials is added to the granulator; and (v) the new mixture obtained is agglomerated in the granulator in order to obtain granules (b). This sequenced granulation process allows granules to be obtained that have a degree of moisture that assures their stability and their ease of handling eliminating the drying step.

Abstract: Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approaches: in one exemplary embodiment, the first approach comprises canonicalizing the “regular” 32-bit instruction addressing modes, and the second for the “compressed” 16-bit instruction addressing modes. In another aspect, a plurality of functions (up to and including all available functions) are called indirectly to allow addresses to be placed in a constant pool. Improved methods for instruction selection, register allocation and spilling, and instruction compression are provided. An improved SoC integrated circuit device having an optimized 32-bit/16-bit processor core implementing at least one of the foregoing improvements is also disclosed.

Abstract: An improved method and apparatus for performing single-cycle operations (such as for example Maximum a Posteriori, i.e. MAP decode) in digital processors is disclosed. In one exemplary configuration, a processor is fitted with a specialized instruction and extension Arithmetic Logic Unit (ALU) to efficiently perform the forward and reverse transition trellis metric updates as well as the Log Likelihood ratio calculation in order to accelerate the decoding of Turbo-encoded data sequences. The processor executes software comprising the single operand instruction to perform Turbo decoding with the efficiency comparable to a dedicated hardware implementation. The programmable apparatus can be readily reprogrammed to accommodate evolving standards.

Abstract: An improved method and apparatus for controlling and implementing instructions in a pipelined central processing unit (CPU) or user-customizable microprocessor. In a first aspect of the invention, an improved method of permitting programmer control of jump instruction interlocks is disclosed. In one embodiment, a minimum of one cycle is required between an instruction that sets flags and a branch taken as a result of those flags; an interlock is used to detect a branch preceded by an instruction setting the flags to ensure that the instruction immediately preceding the branch can not affect the branch outcome. In a second embodiment, a jump instruction following a flag setting instruction whose flags may affect the outcome of the jump is stalled until all flags are set. In a second aspect of the invention, a method of synthesizing a processor design incorporating the aforementioned interlocks is disclosed.

Abstract: A method and apparatus for analyzing and formatting strings of data, such as data derived from software processes running on two data processors. In one embodiment, a plurality of different data strings are initialized building a symbol array, and finding differences within the data by analyzing various relationships within the data strings, such as the existence of unique strings. A computer program and apparatus for synthesizing logic implementing the aforementioned methodology are also disclosed.

Abstract: A method and apparatus for debugging programs in a distributed environment, such as a set of heterogeneous hardware processors (integrated circuits or In-Circuit Emulators), and/or software-based simulators. In one embodiment, the method comprises identifying a plurality of processes; initializing each of the processes; executing with a single thread of control among the processes; and continuously cycling among the processes to obtain status information. A computer program and apparatus for implementing the aforementioned methodology are also disclosed.

Abstract: An improved method of optimizing the instruction set of a digital processor using code compression. In one embodiment, the method comprises obtaining an assembly language program to be used for the optimization process; calculating the static frequency of each instruction type from the base instruction set; sorting the instruction types by frequency; determining the number and type of instructions necessary for correct program execution; creating a compressed instruction set encoding; re-evaluating the compressed instruction according to the foregoing steps; and generating an instruction set encoding for the compressed instruction set. Improved compressed instruction formats and register structures useful in a processor are also disclosed. A computer program and apparatus for synthesizing logic implementing the aforementioned data cache architecture and pipeline performance enhancements are further disclosed.

Abstract: An improved method and apparatus for performing operations (such as Viterbi decode) in digital processors using a reduced number of cycles. In one aspect, the invention comprises efficient methods for performing multiple “butterfly” add-compare-select (ACS) operations using an improved dual butterfly (DVBF) extension instruction added to the instruction set of a user-configured processor. The DVBF extension allows performance of two butterfly operations in a single cycle. In another aspect, an improved path metric addressing scheme is disclosed. An integrated circuit (IC) device incorporating the aforementioned features, and method of designing such IC, are also disclosed.

Abstract: An apparatus and method for performing enhanced algorithmic processing, including reduced cycle-count fast Fourier transform (FFT) calculations. In one aspect, the invention comprises a user-configurable processor having an extension instruction adapted for reduced cycle-count algorithmic operations. In one exemplary embodiment, the processor is an extensible core, and the extension instruction comprises a 32-bit instruction word linked with existing circuitry in the processor core used for multiply-accumulate (mac) instructions. 16-bit, 24-bit, and dual 16-bit multiply options are available for the multiply/accumulate unit of the processor. The extension instruction is pipelined to the same number of stages as the mac instructions, thereby avoiding unnecessary stalls and increasing performance. A modified accumulator data path used in support of the foregoing instruction is also described.

Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.

Abstract: A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

Abstract: An improved method and apparatus for performing single-cycle operations (such as Viterbi decode) in digital processors is disclosed. In one aspect, the invention comprises methods for storing (“packing”) old and new metric data in memory that cooperate with a single-operand instruction adapted to perform single cycle calculations such as the Viterbi butterfly. Accordingly, such calculations can be computed effectively in software in a single cycle. In another aspect, an improved memory addressing mode is used to write back two new output results at the completion of instruction execution. The improved packing of state metrics in memory, single-operand instruction, and addressing mode can advantageously be integrated into any processor (e.g., DSP, RISC-DSP, or configurable processor) with appropriate memory. The user of such a processor may accordingly write software using the single-operand instruction to perform Viterbi decode with the efficiency comparable to a dedicated hardware implementation.

Abstract: An improved method and apparatus for performing single-cycle operations (such as for example Maximum a Posteriori, i.e. MAP decode) in digital processors is disclosed. In one exemplary configuration, a processor is fitted with a specialized instruction and extension Arithmetic Logic Unit (ALU) to efficiently perform the forward and reverse transition trellis metric updates as well as the Log Likelihood ratio calculation in order to accelerate the decoding of Turbo-encoded data sequences. The processor executes software comprising the single operand instruction to perform Turbo decoding with the efficiency comparable to a dedicated hardware implementation. The programmable apparatus can be readily reprogrammed to accommodate evolving standards.