Abstract: A one-wire clock-skew compensating method and a circuit for the method are disclosed to solve the clock-skew problem in transmission of clock signals in a high-speed synchronous circuit such as of a CPU, hence the clock of a remote circuit and the clock input of the system can be accurately synchronized. The method is based on the principle of identical propagation delay on the forward and reverse paths at the two ends of one wire in transmission and receiving; a clock-deskew buffer composing a delay locked loop and a bidirectional buffer is provided in the front of the signal transmission end of the wire, while the other end of the wire has a bidirectional buffer too, hence signals are transmitted bidirectionally at the same time on the wire.