Abstract: An electronic design automation tool embodiment of the present invention comprises a five step process. In a first step, for each pin-master of arbitrary shape in a cell-master a pin access direction is identified, a region in which placing a via will connect a pin to a metal layer, and cause no design rule violation to other pin-masters, is physical bounded on the surface of a chip. Such a region is defined to be a "via-region" of the pin-master. In a second step, at least one "via-spot" within each via-region is identified that violates no design rules if vias are placed at these points. In a third step, vias are placed on each cell instance according to their via-spots. In a fourth step, a "maze-routing" is done to connect the neighboring same net pins by metal-1. In a fifth step, the vias on the pins connected by the maze-router are removed, leaving only one via on a pin if the connection for a current net is not complete.

Abstract: An electronic design automation tool embodiment uses a single slack graph structure throughout a process to provide communication between a placer (performing placement) and a timing constraint generator (performing slack distribution). The tool includes a slack graph generator, a timing calculator, a timing analyzer, a timing constraint generator and a net bounding box generator. A list of net constraints and a list of complete path constraints are fed to the slack graph generator during operation. Timing calculations from the delay calculator and zero net RC delays from a clustering process in a placer also provide input to the slack graph generator. The list of net constraints, a list of pin-to-pin constraints and a set of specifications for system clocking are input to the timing analyzer. The timing constraint generator receives a composite slack graph from the timing calculator, slack graph generator and timing analyzer.